[2023-03-24] Dr.Tse-Yu Yeh,VP of Silicon Engineering at Rivos,"My path in the silicon engineering area"

  • 2023-03-23
  • 宋欣薏(職務代理)

Title: My path in the silicon engineering area
2023-03-24 14:20-15:30
Location:  CSIE R103
er: Dr. Tse-Yu Yeh(葉則昱), VP of Silicon Engineering at Rivos
Hosted by: 
Prof. Chia-Ling Yang

Tse-yu will mainly share his path in the silicon engineering area.

Tse-Yu Yeh is the VP of Silicon Engineering of Rivos Inc.Rivos is a multi-national start-up company targeting towards integrated hardware, software, and chip design for server applications in data analytics and machine learning. Prior to his position at Rivos Inc., he was the Senior Director of the high performance PU design group at Apple. He managed the team delivered the high performance PUs in M series of SOCs and A series of SOCs. He uilt the CPU design team up from the initial team acquired from P.A. Semi. At .A. Semi he was the Senior Director of CPU architecture and SOC verification. He also worked at Broadcom as the senior manager in the Broadband processor division and the CPU architect at SiByte. He started his career at Intel as the IA-64 front end architect, microarchitect, and verification manager.
He received his PhD from the Electrical Engineering and Computer Science Department at the University of Michigan. His research focused on the out of order execution and branch prediction. In 2007, one of his papers on Two-level branch prediction published in 1992 was selected to be among the most influential papers in International Symposium of Computer Architecture.