Date：2025/12/12 15:40-17:00
Location：R103, CSIE
Speakers：Prof. Hung-Wei Tseng
Host：楊佳玲教授
Abstract:
The rise of domain-specific computing has led to a proliferation of Domain-Specific Accelerators (DSAs). While hardware for tasks like machine learning and ray tracing offers immense performance, this trend risks "Balkanizing" the silicon, where each specialized unit occupies valuable die area but often sits idle. This talk challenges this single-use paradigm, proposing a shift toward "multi-domain accelerators": hardware units that are intelligently extended to efficiently service applications from several, often algorithmically adjacent, domains. This approach promises the performance of specialization while retaining a high degree of hardware utilization and efficiency.
We will use the modern Ray-Tracing Accelerator (RTA), a fixture in contemporary GPUs, as our central case study. Natively designed for graphics, the RTA's core competency—accelerating hierarchical Bounding Volume Hierarchy (BVH) tree traversals—shares fundamental properties with other challenging computational problems. We will first explore the "Tree Traversal Accelerator" (TTA), which generalizes the RTA. By introducing modest programmability and new fixed-function logic, the TTA extends the RTA to accelerate a new domain of general-purpose tree traversal applications, including database indexing (B-Trees) and N-Body physics simulations, achieving significant speedups.
Next, we demonstrate this is not an isolated case by examining the RT+SpMSpM architecture, which adapts the same RTA for a completely different domain: sparse matrix-matrix multiplication (SpMSPM). This work identifies that the irregular memory access and control flow divergence in SpMSPM mirror the challenges of ray tracing. It shows how, with minimal hardware modifications to reuse existing multipliers and add an accumulation engine, the RTA can be repurposed to dramatically accelerate sparse matrix algebra. These two examples compellingly show how a single accelerator, with minimal, intelligent modifications, can be transformed from a single-domain unit into a multi-domain workhorse, providing a sustainable and efficient path forward for heterogeneous computing.
We will use the modern Ray-Tracing Accelerator (RTA), a fixture in contemporary GPUs, as our central case study. Natively designed for graphics, the RTA's core competency—accelerating hierarchical Bounding Volume Hierarchy (BVH) tree traversals—shares fundamental properties with other challenging computational problems. We will first explore the "Tree Traversal Accelerator" (TTA), which generalizes the RTA. By introducing modest programmability and new fixed-function logic, the TTA extends the RTA to accelerate a new domain of general-purpose tree traversal applications, including database indexing (B-Trees) and N-Body physics simulations, achieving significant speedups.
Next, we demonstrate this is not an isolated case by examining the RT+SpMSpM architecture, which adapts the same RTA for a completely different domain: sparse matrix-matrix multiplication (SpMSPM). This work identifies that the irregular memory access and control flow divergence in SpMSPM mirror the challenges of ray tracing. It shows how, with minimal hardware modifications to reuse existing multipliers and add an accumulation engine, the RTA can be repurposed to dramatically accelerate sparse matrix algebra. These two examples compellingly show how a single accelerator, with minimal, intelligent modifications, can be transformed from a single-domain unit into a multi-domain workhorse, providing a sustainable and efficient path forward for heterogeneous computing.
Biography:
Hung-Wei Tseng currently an associate professor in the Department of Electrical and Computer Engineering and a cooperating faculty of the Department of Computer Science and Engineering at University of California, Riverside, where Hung-Wei is now leading the Extreme Scale & Computer Architecture Laboratory.
Hung-Wei Tseng is interested in designing architecture, programming language frameworks, and system infrastructures that allow applications and programmers to use modern heterogeneous hardware components more efficiently. Hung-Wei's recent focus is on using AI/ML accelerators and ray-tracing hardware to improve the performance of applications beyeond AI/ML and graphics domains. Hung-Wei Tseng's research has been recognized by IEEE MICRO Top Picks From Computer Architecture Conferences in 2024 and 2020.
Hung-Wei Tseng is interested in designing architecture, programming language frameworks, and system infrastructures that allow applications and programmers to use modern heterogeneous hardware components more efficiently. Hung-Wei's recent focus is on using AI/ML accelerators and ray-tracing hardware to improve the performance of applications beyeond AI/ML and graphics domains. Hung-Wei Tseng's research has been recognized by IEEE MICRO Top Picks From Computer Architecture Conferences in 2024 and 2020.
Hung-Wei Tseng
Associate Professor, Department of Electrical and Computer Engineering
Cooperating Faculty, Department of Computer Science and Engineering
University of California, Riverside
http://intra.engr.ucr.edu/~htseng/