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Figure 4(a) -- Interrupt service addressing in Real Mode
 
 
 
 
 
 
 
Fig 4(b) Interrupt service addressing in Protected Mode
 
 
 
 


 

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Table 1 -- Exceptions and Interrupts
Description Int # Type Return Addr points to faulting instruction Error Code This interrupt first appeared in this CPU
Division by 0 
Debug Exception 
NMI 
Breakpoint 
Overflow 
Bounds 
Invalid OP Code 
Device not available 
Double Fault 
Copr. segment overrun 
Invalid TSS 
Segment not present 
Stack fault 
General Protection 
Page fault 
Floating point error 
Alignment check 
Machine check 
Software interrupts










10 
11 
12 
13 
14 
16 
17 
18 
0-255
Fault 
*1 
*2 
Trap 
Trap 
Fault 
Fault 
Fault 
Abort 
Fault 
Fault 
Fault 
Fault 
Fault 
Fault 
Fault 
Fault 
Abort 
Trap
Yes 
*1 
No 
No 
Yes 
Yes 
Yes 
Yes 
No 
Yes 
Yes 
Yes 
Yes 
Yes 
Yes 
Yes 
Yes 
No 
No
No 
No 
No 
No 
No 
No 
No 
No 
Yes 
No 
Yes 
Yes 
Yes 
Yes 
Yes 
No 
Yes 
Yes 
No
8086 
8086 
8086 
8086 
8086 
80186 
80186 
80186 
80286 
80286 *3 
80286 
80286 
80286 
80286 
80386 
80386 
80486 
Pentium *4 
All
*1  On the 386-class CPUs, debug exception can be either traps, or faults. A trap is caused by the Trap Flag (TF) being set | in the flags image, or using the debug registers to generate data breakpoints. In this case the return address is the instruction following the trap. Faults are generated by setting the debug registers for code execution breakpoints. As with all faults, the return address points to the faulting instruction.
*2 Non-maskable.
*3 Removed from the 80486, now generates exception 13 on all future processors.
*4 Model dependant. Behavior may be different or missing on future processors.