DESCRIPTOR CACHE REGISTERS

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Figure 2 (a) 80286 Descriptor Cache Register
[47..32] 31 [30..29] 28 [27..25] 24 [23..00]
16-bit Limit P DPL S Type A 24-bit base address
 
 
Figure 2 (b) 80386/80486 Descriptor Cache Register
[31..24] 23 [22..21] 20 [19..17] 16 15 14 [13..00]
0 P DPL S Type A 0 D 0
 
 
[63..32]
32-bit Physical Address
 
 
[95..64]
32-bit Limit
 
 


                                                     Figure 3 -- Descriptor Cache Contents (Real Mode)
 

 
 
 

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