[2017-12-15] Prof. Yiran Chen, Duke University ,"Running sparse and low-precision neural networks: when algorithm meets hardware”

Poster:Post date:2017-12-15

Title: Running sparse and low-precision neural networks: when algorithm meets hardware
Date: 2017-12-15 11:00am-12:00pm
Location: R104, CSIE
Speaker: Prof. Yiran Chen, Duke University
Hosted by: Prof. Tei-Wei Kuo


Rapidly increase of computation cost consumed in training and testing of deep neural networks (DNNs) inspired many acceleration techniques. Reducing topological complexity and data representation of neural networks are two approaches popularly adopted in deep learning algorithm society. In general, many connections in DNNs can be pruned and the synaptic weights can be represented using low-precision without/with minimum impact on inference accuracy. However, these algorithm-level techniques often ignore the practical scenarios when they are deployed onto hardware computing platforms, e.g., the increase in the random accesses to memory hierarchy. On the contrary, hardware society often has limited understanding about the expectations from algorithm society and hence, makes many unrealistic assumptions during hardware designs. In this talk, we will discuss this mismatch and show how we can solve this problem through an interactive design practice across both software and hardware regimes.




Yiran Chen received B.S and M.S. (both with honor) from Tsinghua University and Ph.D. from Purdue University in 2005. After five years in industry, he joined University of Pittsburgh in 2010 as Assistant Professor and then promoted to Associate Professor with tenure in 2014, held Bicentennial Alumni Faculty Fellow. He now is an tenured Associate Professor of the Department of Electrical and Computer Engineering at Duke University and serving as the co-director of Duke Center for Evolutionary Intelligence (CEI), focusing on the research of new memory and storage systems, machine learning and neuromorphic computing, and mobile computing systems. Dr. Chen has published one book and more than 300 technical publications. He has been granted 93 US and international patents with other 10 pending applications. He is the associate editor of IEEETNNLS, IEEE TCAD, IEEE D&T, IEEE ESL, ACM JETC, ACM TCPS, and served on the technical and organization committees of more than 40 international conferences. He received 5 best paper awards and 15 best paper nominations from international conferences. He is the recipient of NSF CAREER award and ACM SIGDA outstanding new faculty award, and elected to the Fellow of IEEE very recently.


Last modification time:2017-12-15 AM 11:05

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