Chia-Lin Yang

       Professor
       Department of Computer Science and
Information Engineering
       National Taiwan University
      
No. 1, Roosevelet Rd., Sec 4
       Taipei, Taiwan 106, R.O.C
       Tel: 886-2-23625336
       Fax: 886-2-23628167
       Email: yangc@csie.ntu.edu.tw


本實驗室目前積極招生中

 

Research LAB: Embedded Computing Lab

Research Interests:

Courses I Teach:

·         Low-Power System Design (Fall 2009)

·         Advanced Computer Architecture (Fall 2009)

·         Introduction to Embedded System (Fall 2006)

·         Computer Architecture and Organization (Spring 2009)

 


Publications:

Journal Papers

·         Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips, Ping-Hung Yuh, Sachin Sapatnekar, Chia-Lin Yang, Yao-Wen Chang,  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 9, pp. 1295-1306, 2009 (SCI)

·        Ping-Hung Yuh,  Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin, Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs,  ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 14, no. 4, article 52, 2009,

·         Ping-Hung Yuh,   Chia-Lin Yang, Yao-Wen Chang,T-trees: A Tree-Based Representation for Temporal and Three-Dimensional Floorplanning,.  ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 4, Article 51, 2009

·         Yi-Jung Chen, Chia-Lin Yang and Yen-Sheng Chang, An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, Journal of Systems Architecture, vol. 55,  Issues 5-6, pp. 299-309, 2009  (SCI)

·         Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang and Yu-Jung Cheng, A Predictive Shutdown Technique for GPU Shader Processors,  IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 9-12, 2009, (EI)

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, Y.-J. Chen, C.-L. Yang and Y.-S. Chang, to appear in Journal of Systems Architecture. (SCI) (accepted on 03/04/2009)

·         A Predictive Shutdown Technique for GPU Shader Processors, P.-H. Wang, Y.-M. Chen, C.-L. Yang and Y.-J. Cheng, to appear in IEEE Computer Architecture Letters, Vol. 8, 2009, (EI) (13 Jan. 2009. IEEE Computer Society Digital Library)

·         A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters, S.-W, Wang, S.-S Yang, H.-M, Chen, C.-L, Yang, W.-J, Ling, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, (SCI) (published online: 12/04/2008)

·         BioRoute: A Network-Flow Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008.

·         Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.-L. Yang, H.-W., Tseng, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

·         Placement of Defect-Tolerant Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC)

·         Temporal Floorplanning Using the Three Dimensional Transitive Closure SubGraph, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, to appear in ACM Transaction on Design Automation of Electronic Systems (TODAES)

·         Software-Controlled Cache Architecture for Energy Efficiency, C.-L. Yang, H.-W. Tseng, C.-C. Ho, J.-L. Wu, IEEE Trans. Circuits Syst. Video Techn. 15(5),  634-644,  May, 2005

·         Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications, C.-L. Yang, A. R. Lebeck, H.-W. Tseng, and C.-H. Lee, ACM Transacations on Architecture and Code Optimization, 1(4),  445-475, December, 2004

·         Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero, Y,-J, Chang, F. Lai and C.-L Yang, in IEEE Transactions on Very Large Intergration (VLSI) Systems, 12(8), August, 2004

·         Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C.-L. Yang, B. Sano, and A. R. Lebeck, In IEEE Transactions on Computers, 49(9), September, 2000

Conference Papers

·         Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu, Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling, ACM/IEEE International Conference on Computer-Aided Design (ICCAD '09) , November, 2009, Best Paper Nomination

·         Chung-Hsiang Lin,  Chia-Lin Yang, Ku-Jei King, PPT: Joint Performance/Power/Thermal Management of DRAM Memory for Multi-Core Systems,IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09) , August, 2009, Best Paper Award

·         Yi-Chan Li, Hsiu-Hsien Li, Han-Lin Li, Chia-Lin Yang, Content-Aware Energy Prediction for Video Streaming in Mobile Devices, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April, 2009

·         Content-Aware Energy Prediction for Video Streaming in Mobile Devices, Y.-C. Li, H.-H. Li, H.-L. Li, C.-L. Yang, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April, 2009

·         A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips, P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, in Proceedings of ACM/IEEE Design Automation conference (DAC’08), pp. 284-289, Anaheim, CA, USA, June, 2008 (EI) (acceptance rate: 23%, 147/239)

·         Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAs, C-F. Li, P-H. Yuh. C-L. Yang and Y-W. Chang, in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '07),Portland,USA, August, 2007

·         Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, ans Y.-W. Chang, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD '07),San Jose,CA, November, 2007

·         Cache Leakage Control Mechanism for Hard Real-Time Systems, J.-W. Chi, Y.-J. Chen, and C.-L. Yang, in Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), Saizburg, Austria, September, 2007.

·         Energy-Efficient Real-Time Task Scheduling with Task Rejection, J.-J. Chen, T.-W. Kuo, C.-L. Yang and K.-J. King, in Proceedings of Design, Automation & Test in Europe (DATE '07), Nice, France, April, 2007

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, W.-H. Hung, Y.-J. Chen, C.-L. Yang, Y.-S. Chang, Alan P. Su, in Proceedings of 22nd Annual ACM Symposium on Applied Computing (SAC '07), Seoul, Korea, March, 2007

·         An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, H.-W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006

·         Hierarchical Value Cache Encoding for Off-chip Data Bus, C.-H. Lin and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006

·         Placement of Digital Microfluidic Biochips Using the T-Tree Formuation, P-H. Yuh, C.-L. Yang,and Y.-W. Changn, in Proceedings of ACM/IEEE Design Automation Conference (DAC '06), San Franciso, CA, July, 2006

·         A Space Efficient Caching Mechanism for Flash Memory Address Translation, C.-H. Wu, T.-W Kuo and C.-L Yan, in Proceedings of IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC '06), Gyeongju, Korea, April, 2006

·         Cache Leakage Management for Multi-programming Workloads, C.-. Chen, C.-L. Yang, S.-H. Hung, in Proceedings of Asia-Pacific Computer Systems Architecture Conference (ACSAC '05), Singapore, October, 2005

·         Reconfigurable Platform for Content Science Research, C.-S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien,Y.-W. Chang, L.-G. Chen, in Proceedings of Embedded and Real-Time Computing Systems and Applications (RTCSA '05), Hong Kong, August, 2005 

·         Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration, Y.-W. Wu, C.-L. Yang, P.-H. Yuh,Y.-W. Chang, in Proceedings of the 2005 international symposium on Low power electronics and design (ISLPED '05), Sandiego, USA, August, 2005

·         Phase-Aware I-Cache Size Synthesis with QoS Consideration, Y.-J. Chen, C.-L. Yang, E.-K. Lin, in Proceedings of Asia and South Pacific International Conference on Embedded SoCs (ASPICES '05), Banagolore, India, July, 2005

·         Workload Characterization of the H.264/AVC Decoder, C.-L. Yang, in Proceedings of the 5th IEEE Pacific-Rim Conference on Multimedia (PCM '04), Springer-Verlag, Japan, November, 2004

·         Temporal Floorplanning using T-tree Formulation, P.-H. Yu, C.-L. Yang andY.-W. Chang, in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD '04), San Jose, November, 2004

·         Energy-Efficient Flash Memory Storage Systems with an Interrupt Emulation Mechanism, C.-H. Wu, T.-W Kuo and C.-L Yang, in Proceedings of IEEE/ACM International Conference on Hardware/Software odesign and System Synthesis (CODES + ISSS '04),Stockholm, Sweden, September, 2004

·         HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction, C.-L. Yang and C.-H. Lee, in Proceedings of IEEE/ACM Internatioanl Symposium on Low Power Electronics and Design (ISLPED '04), NewPort Beach, California, August, 2004

·         Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations, J.-J. Chen, H.-R. Hsu, K.-H. Chuang, C.-L. Yang, A.-C. Pang and T.-W. Kuo, in Processdings of 16th Euromicro Conferecne on Real-Time Systems (ECRTS'04), Catania, Italy, June, 2004

·         Profit-Driven Uniprocessor Scheduling with Energy and Timing Constraints, J.-J. Chen, T.-W. Kuo and C.-L. Yang. In Proceedings of the in Proceedings of 19nd Annual ACM Symposium on Applied Computing (SAC '04), Nicosia, Cyprus, March, 2004

·         Value-Conscious Cache: Simple Technique for Reducing Cache Access Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '04), Paris, France, February, 2004

·         Temporal Floorplanning Using 3D-subTCG, P.-H. Yuh, C.-L. Yang andY.-W. Chang, in Proceedings of 9th Asia and South Pacific Design Automation Conference (DATE '04), Seoul, Korea, January, 2004

·         Smart Cache: An Energy-Efficient D-Cache for a Software MPEG-2 Video Decoder, C.-L. Yang, H.-W. Tseng and C.-C. Ho. In Proceedings of the IEEE ICICS-PCM, Singapore, December 2003

·         A Power-Ware SWRD Cell for Reducing Cache Write Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design (ISPLED '03), Seoul, Korea, August, 2003

·         Using Intel Streaming SIMD Extensions for 3D Geometry Processing, W. Ma and C.-L. Yang, in Proceedings of the 3th IEEE Pacific-Rim Conference on Multimedia (PCM '02), Springer-Verlag, Taiwan, December, 2002

·         A Programmable Memory Hierarchy for Prefetching Linked Data Structures, C.-L. Yang and A. R. Lebeck, in Proceedings of the 4th International Symposium on High Performance Computing (ISHPC-IV), Springer-Verlag, Japan, May, 2002

·         Push vs. Pull: Data Movement for Linked Data Structures, C.-L. Yang and A. R. Lebeck, International Conference on Supercomputing 2000 (ICS '00), May, 2000.

·         Annotated Memory References: A Mechanism for Informed Cache Management , A. R. Lebeck, D. R. Raymond, C.-L. Yang, M. S. Thottethodi, Euro-Par '99, August, 1999. (Short Version)

·         Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, C.-L. Yang, B. Sano, and A. R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO '98), November

Technical Reports

·         HotSpot Cache: Saving I-Cache Energy with Dynamic Program Hot Spot Detection for Multimedia Applications

, C.-L. Yang, C.-H. Lee, In Technical Report (TK-03-03) of Department of Computer Science and Information Engineering,National Taiwan University.


Education:

·         Ph.D., Computer Science,Duke University, 2001

·         M.S., Computer Science, University ofTexas at Austin, 1992

·         B.Ed., Information & Computer Education,National Taiwan Normal University, 1990


Experiences:

·         Summer Intern, Western Research Lab, Compaq Corp., Summer 1997

·         Summer Intern, Apple Computer, Inc., Summer 1996

·         Software Engineer, VLSI Technology Corp., 1993-1995


Awards:

·         Duke Fellowship Award, 1995

·         2000-2001 Intel Foundation Graduate Fellowship Award

·         NTU Excellent Teaching Award 2003國立台灣大學93年度教學優良獎

·         IBM Faculty Award 2005     

·         2009 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09) 最佳論文獎

·         2009 ACM/IEEE International Conference on Computer-Aided Design (ICCAD '09) 最佳論文獎提名

·         Advisory Award 論文指導 

            2004 Acer Dragon Thesis Award 第十八屆宏碁龍騰知識經濟論文優等獎

2004 CIEE Master Thesis Award 93年度中國電機工程學會青年論文獎第三名

2004 IICM Master Thesis Award 93年度中華民國資訊學會碩士論文佳作

94CIEE Master Thesis Award 94度中國電機工程學會青年論文獎第三名

2005 IICM Master Thesis Award 94年度中華民國資訊學會碩士論文獎