Chia-Lin Yang

       Professor
       Department of Computer Science and Information Engineering
       National Taiwan University
       No. 1, Roosevelet Rd., Sec 4
       Taipei, Taiwan 106, R.O.C
       Tel: 886-2-23625336
       Fax: 886-2-23628167
       Email: yangc@csie.ntu.edu.tw

本實驗室目前積極招生中

Research LAB: Embedded Computing Lab

Research Interests:

• Multi-core architecture: Programming tool, Design and Analysis
   
• GPU architecture design
   
• MPSOC: Tool, Analysis and Design
   
• Next-Generation NVM Storage System
   

Courses I Teach:

·         Topics in Low Power System (Fall 2010)

·         Advanced Computer Architecture (Fall 2010)

·         Introduction to Embedded System (Fall 2006)

·         Computer Architecture and Organization (Spring 2011)

Publications:

Journal Papers

·         TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems, to appear in IEEE Transactions on Computer

·         A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips, P.-H. Yuh, Sachin Sapatnekar, C.-L. Yang, Y.-W. Chang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(9), 1295-1306, 2009.

·        Leakage-aware Task Scheduling for Partially Dynamically Reconfigurable FPGAs, P.-H. Yuh,  C.-L. Yang, C.-F. Li, C.-H. Lin, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4), article 52, August, 2009.

·         T-trees: A Tree-Based Representation for Temporal and Three-Dimensional Floorplanning, P.-H. Yuh,   C.-L. Yang, Y.-W. Chang, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4), article 51, August, 2009.

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, Y.-J. Chen, C.-L. Yang and Y.-S. Chang, in Journal of Systems Architecture, 55(5-6), 299-309, May, 2009.

·         A Predictive Shutdown Technique for GPU Shader Processors, P.-H. Wang, Y.-M. Chen, C.-L. Yang and Y.-J. Cheng, in IEEE Computer Architecture Letters, 8(1), 9-12, 2009.

·         A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters, S.-W, Wang, S.-S Yang, H.-M, Chen, C.-L, Yang, W.-J, Ling, in Journal Signal Processing Systems, 57(2), 195-211, November, 2009.

·         BioRoute: A Network-Flow Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(11), 1928-1941, 2008

·         Energy-Aware Flash Memory Management in Virtual Memory System, L.-H. Lin, C.-L. Yang, H.-W., Tseng, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(8), 952-964, August, 2008.

·         Placement of Defect-Tolerant Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Journal on Emerging Technologies in Computing Systems (JETC), 3(3), article 13, November, 2007.

·         Temporal Floorplanning Using the Three Dimensional Transitive Closure SubGraph, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Transaction on Design Automation of Electronic Systems (TODAES), 12(4), article 37, September, 2007..

·         Software-Controlled Cache Architecture for Energy Efficiency, C.-L. Yang, H.-W. Tseng, C.-C. Ho, J.-L. Wu, in IEEE Transaction on Circuits and Systems for Video Technology, 15(5), 634-644, May, 2005.

·         Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications, C.-L. Yang, A. R. Lebeck, H.-W. Tseng, and C.-H. Lee, in ACM Transacations on Architecture and Code Optimization, 1(4),  445-475, December, 2004.

·         Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero, Y,-J, Chang, F. Lai and C.-L Yang, in IEEE Transactions on Very Large Intergration (VLSI) Systems, 12(8), August, 2004.

·         Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C.-L. Yang, B. Sano, and A. R. Lebeck, in IEEE Transactions on Computers, 49(9), 934-946, September, 2000.

    Conference Papers

·         Memory Latency Reduction via Thread Throttling, H. -Y Cheng, C.-H Lin, J. Lee , C.-L Yang, in Proceedings of IEEE International Symposium on Microarchitecture (Micro’10), Atlanta, Georgia, USA, December

·         PHierarchical Memory Scheduling for Multimedia MPSoCs, Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang and Naehyuck Chang,Proceedings of the 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

·         Parallelization and Characterization of GARCH Option Pricing on GPUs, Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang,Proceedings of the 2010 IEEE International Symposium on Workload Characterization (IISWC).

·         PM-COSYN: PE and Memory Co-Synthesis for MPSoCs hermal Modeling for 3D-ICs with Integrated Microchannel Cooling, Y.-J. Chen, C.-L. Yang and P.-H. Wang, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '10), Dresden, Germany, March, 2010.

·         Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling, H. Mizunuma, C.-L. Yang, Y.-C. Lu, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD '09) , San Jose, CA, USA, November, 2009, Best Paper Nomination.

·         PPT: Joint Performance/Power/Thermal Management of DRAM Memory for Multi-Core Systems, C.-H. Lin,  C.-L. Yang, K.-J. King, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09), San Francisco, CA, USA, August, 2009, Best Paper Award.

·         Content-Aware Energy Prediction for Video Streaming in Mobile Devices, Y.-C. Li, H.-H. Li, H.-L. Li, C.-L. Yang, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April, 2009.

·          A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips, P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, in Proceedings of ACM/IEEE Design Automation conference (DAC’08), Anaheim, CA, USA, June, 2008 (EI) (acceptance rate: 23%, 147/239).

·         Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAs, C-F. Li, P-H. Yuh. C-L. Yang and Y-W. Chang, in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '07), Portland, USA, August, 2007.

·         Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, P.-H. Yuh, C.-L. Yang, ans Y.-W. Chang, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD'07),San Jose, CA, November, 2007.

·         Cache Leakage Control Mechanism for Hard Real-Time Systems, J.-W. Chi, Y.-J. Chen, and C.-L. Yang, in Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), Saizburg, Austria, September, 2007.

·        Energy-Efficient Real-Time Task Scheduling with Task Rejection, J.-J. Chen, T.-W. Kuo, C.-L. Yang and K.-J. King, in Proceedings of Design, Automation & Test in Europe (DATE '07), Nice, France, April, 2007.

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, W.-H. Hung, Y.-J. Chen, C.-L. Yang, Y.-S. Chang, Alan P. Su, in Proceedings of 22nd Annual ACM Symposium on Applied Computing (SAC '07), Seoul, Korea, March, 2007.

·         An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, H.-W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006.

 ·         Hierarchical Value Cache Encoding for Off-chip Data Bus, C.-H. Lin and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006.

·         Placement of Digital Microfluidic Biochips Using the T-Tree Formuation, P-H. Yuh, C.-L. Yang,and Y.-W. Changn, in Proceedings of ACM/IEEE Design Automation Conference (DAC '06), San Franciso, CA, July, 2006.

·         A Space Efficient Caching Mechanism for Flash Memory Address Translation, C.-H. Wu, T.-W Kuo and C.-L Yan, in Proceedings of IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC '06), Gyeongju, Korea, April, 2006.

·         Cache Leakage Management for Multi-programming Workloads, C.-. Chen, C.-L. Yang, S.-H. Hung, in Proceedings of Asia-Pacific Computer Systems Architecture Conference (ACSAC '05), Singapore, October, 2005.

·         Reconfigurable Platform for Content Science Research, C.-S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien,Y.-W. Chang, L.-G. Chen, in Proceedings of Embedded and Real-Time Computing Systems and Applications (RTCSA'05), Hong Kong, August, 2005.

·         Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration, Y.-W. Wu, C.-L. Yang, P.-H. Yuh,Y.-W. Chang, in Proceedings of the 2005 international symposium on Low power electronics and design (ISLPED '05), Sandiego, USA, August, 2005.

·         Phase-Aware I-Cache Size Synthesis with QoS Consideration, Y.-J. Chen, C.-L. Yang, E.-K. Lin, in Proceedings of Asia and South Pacific International Conference on Embedded SoCs (ASPICES '05), Banagolore, India, July, 2005.

·        Workload Characterization of the H.264/AVC Decoder, C.-L. Yang, in Proceedings of the 5th IEEE Pacific-Rim Conference on Multimedia (PCM '04), Springer-Verlag, Japan, November, 2004.

·        Temporal Floorplanning using T-tree Formulation, P.-H. Yu, C.-L. Yang andY.-W. Chang, in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), San Jose, November, 2004.

·         Energy-Efficient Flash Memory Storage Systems with an Interrupt Emulation Mechanism, C.-H. Wu, T.-W Kuo and C.-L Yang, in Proceedings of IEEE/ACM International Conference on Hardware/Software odesign and System Synthesis (CODES + ISSS '04),Stockholm, Sweden, September, 2004.

·         HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction, C.-L. Yang and C.-H. Lee, in Proceedings of IEEE/ACM Internatioanl Symposium on Low Power Electronics and Design (ISLPED '04), NewPort Beach, California, August, 2004.

·         Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations, J.-J. Chen, H.-R. Hsu, K.-H. Chuang, C.-L. Yang, A.-C. Pang and T.-W. Kuo, in Processdings of 16th Euromicro Conferecne on Real-Time Systems (ECRTS'04), Catania, Italy, June, 2004.

·         Profit-Driven Uniprocessor Scheduling with Energy and Timing Constraints, J.-J. Chen, T.-W. Kuo and C.-L. Yang, in Proceedings of the in Proceedings of 19nd Annual ACM Symposium on Applied Computing (SAC '04), Nicosia, Cyprus, March, 2004.

·         Value-Conscious Cache: Simple Technique for Reducing Cache Access Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '04), Paris, France, February, 2004.

·         Temporal Floorplanning Using 3D-subTCG, P.-H. Yuh, C.-L. Yang andY.-W. Chang, in Proceedings of 9th Asia and South Pacific Design Automation Conference (ASP-DAC'04), Japan, Janury, 2004.

·         Smart Cache: An Energy-Efficient D-Cache for a Software MPEG-2 Video Decoder, C.-L. Yang, H.-W. Tseng and C.-C. Ho, in Proceedings of the IEEE ICICS-PCM, Singapore, December 2003.

·         A Power-Ware SWRD Cell for Reducing Cache Write Power, Y.-J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design.(ISPLED '03), Seoul, Korea, August, 2003.

·         Using Intel Streaming SIMD Extensions for 3D Geometry Processing, W. Ma and C.-L. Yang, in Proceedings of the 3th IEEE Pacific-Rim Conference on Multimedia (PCM '02), Springer-Verlag, Taiwan, December, 2002.

·         A Programmable Memory Hierarchy for Prefetching Linked Data Structures, C.-L. Yang and A. R. Lebeck, in Proceedings of the 4th International Symposium on High Performance Computing (ISHPC-IV), Springer-Verlag, Japan, May, 2002.

·         Push vs. Pull: Data Movement for Linked Data Structures, C.-L. Yang and A. R. Lebeck, in Proceedings of International Conference on Supercomputing (ICS '00), May, 2000.

·         Annotated Memory References: A Mechanism for Informed Cache Management, A. R. Lebeck, D. R. Raymond, C.-L. Yang, M. S. Thottethodi, in Proceedings of Euro-Par '99, August, 1999. (Short Version).

·         Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, C.-L. Yang, B. Sano, and A. R. Lebeck, in Proceedings of ACM/IEEE International Symposium on Microarchitecture (MICRO '98), November, 1998.

 Technical Reports

·         HotSpot Cache: Saving I-Cache Energy with Dynamic Program Hot Spot Detection for Multimedia Applications, C.-L. Yang, C.-H. Lee, In Technical Report (TK-03-03) of Department of Computer Science and Information Engineering,National Taiwan University.

Education:

·         Ph.D., Computer Science,Duke University, 2001

·         M.S., Computer Science, University ofTexas at Austin, 1992

·         B.Ed., Information & Computer Education,National Taiwan Normal University, 1989

Experiences:

·         Summer Intern, Western Research Lab, Compaq Corp., Summer 1997

·         Summer Intern, Apple Computer, Inc., Summer 1996

·         Software Engineer, VLSI Technology Corp., 1993-1995

Honors and Awards:

·         2000-2001 Intel Foundation Graduate Fellowship Award

·         2003 NTU Excellent Teaching Award

·         2004 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC’04) Best Paper Nomination

·         2005 IBM Faculty Award

·         2009 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09) Best Paper Award.

·         2009 ACM/IEEE International Conference on Computer-Aided Design (ICCAD'09) Best Paper Nomination

Professional Activities：

·         2011 IEEE International Parallel & Distributed Processing Symposium, Program Committee Member

·         2011 ACM/IEEE International Symposium on Low Power Electronics and Design, Design Contest Chair

·         2009-2011 ACM/IEEE International Symposium on Low Power Electronics and Design, Program Committee Member

·         2008-2010 ACM/IEEE Asia and South Pacific Design Automation Conference, Program Committee Member

·         2006-2008 IEEE International Conference on Computer Design, Program Committee Member

·        2009 IEEE Annual Symposium on VLSI, Program Committee Member

·         2007-2009 IEEE International Conference on Embedded and Real-Time Computing and Applications, Program Committee Member

·         2008 IEEE International Conference on Field-Programmable Technology, Session Chair & Local Arrangement Co-Chair

·         2008 10th Workshop on Computer Techniques for High-Performance Computing, Program Chair

·         2007 IFIP International Conference on Embedded and Ubiquitous Computing, Program Committee Member & Local Arrangement Co-Chair