大頭貼  

   Chia-Lin Yang

       Professor
       Department of Computer Science and
Information Engineering
       National Taiwan University
      
No. 1, Roosevelet Rd., Sec 4
       Taipei, Taiwan 106, R.O.C
       Tel: 886-2-23625336
       Fax: 886-2-23628167
       Email: yangc@csie.ntu.edu.tw


本實驗室目前積極招生中

 

Research LAB: Embedded Computing Lab

Research Interests:

  • Multi-core architecture: Programming tool, Design and Analysis
     
  • GPU architecture design
     
  • MPSOC: Tool, Analysis and Design
     
  • Next-Generation NVM Storage System


Employment History:

·         Director of Graduate Institute of Networking and Multimedia, 2016 ~ present

·         Director, Office of International Affairs, College of EECS, 2013 ~ 2014

·         Associate Chair, Department of Computer Science and Information Engineering, 2012 ~ 2013

·         Professor, Department of Computer Science and Information Engineering, 2009 ~ present

·         Associate Professor, Department of Computer Science and Information Engineering, 2004 ~ 2009

·         Assistant Professor, Department of Computer Science and Information Engineering, 2001 ~ 2004

·         Software Engineer, VLSI Technology Corp., 1993-1995


Education:

·         Ph.D., Computer Science,Duke University, 2001

·         M.S., Computer Science, University ofTexas at Austin, 1992

·         B.Ed., Information & Computer Education,National Taiwan Normal University, 1989


Honors and Awards:

·         2014 NTU EECS Academic Contribution Award

·         2013 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT) Best Paper Nomination

·         2010 IBM Faculty Award

·         2009 ACM/IEEE International Conference on Computer-Aided Design (ICCAD'09) Best Paper Nomination

·         2009 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09) Best Paper Award.

·         2005 IBM Faculty Award

·         2004 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC’04) Best Paper Nomination

·         2003 NTU Excellent Teaching Award

·         2000-2001 Intel Foundation Graduate Fellowship Award


Professional Activities

·         2016 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Chair

·         2016 ACM/IEEE International Symposium on Microarchitecture, General Chair

·         2016 ACM/IEEE International Symposium on Computer Architecture (ISCA), Program Committee Member

·         Editorial Board, IEEE Design and Testing, 2016

·         2017 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

·         2015 ACM/IEEE Design Automation Conference (DAC), Program Committee Member

·         2015 Usenix ATC (Annual Technical Conference), Program Committee Member

·         Guest Editor, IEEE Design and Testing, Special Issue on Cloud Computing for Embedded Systems, 2014

·         2014 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

·         2014 ACM International Symposium of Computer Architecture (ISCA), Publicility Chair

·         2014 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (ISSS+CODES), Program Committee Member

·         2013 ~ 2015 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Committee Member

·         2013 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (ISSS+CODES), Program Committee Member

·         2013 International Conference on Parallel Processing (ICPP), Program Committee Member

·         2013 IEEE International Symposium on Workload Characterization (ISSWC), Program Committee Member

·         2012 IEEE High Performance Computer Architecture (HPCA), Program Committee Member

·         2012 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), TPC Track Chair

·         2012 ACM/IEEE Design Automation and Testing in Europe (Date), Program Committee Member

·         2011 IEEE International Parallel & Distributed Processing Symposium (IPDPS), Program Committee Member

·         2011~2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Design Contest Chair

·         2009-2013 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Program Committee Member

·         2008-2010 ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Program Committee Member


Publications:

Journal Papers

·         Improving ReadPerformance of NAND Flash SSDs by Exploiting Error Locality, Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li,  IEEE Trans. Computers 65(4): 1090-1102 (2016)

·         System-Level Performance and Power Optimization for MPSoC - A Memory-Access Aware Approach, Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang, ACM Transcations on Embedded Computing System,Volume 14 Issue 1, January 2015 

·         SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs, Chung-Hsiang Lin, De-Yu Shen, Yu-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang, ACM Transaction on Computer Architecture and Code Optimization, 12(2): 19 (2015)

·         Power gating strategies on GPUs, Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen and Yu-Jung Cheng, in ACM Transactions on Architecture and Code Optimizations, 8(3), Article 13, October, 2011.

·         Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling, Mizunuma H, Yi-Chang Lu and Chialin Yang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(9), pp.1293-1306, September, 2011.

·         TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems, Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi and Jian-Jia Chen, in IEEE Transactions on Computers, 60(6), pp.767-782, June 2011.

·         A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips, P.-H. Yuh, Sachin Sapatnekar, C.-L. Yang, Y.-W. Chang,in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(9), 1295-1306, 2009.

·         Leakage-aware Task Scheduling for Partially Dynamically Reconfigurable FPGAs, P.-H. Yuh,  C.-L. Yang, C.-F. Li, C.-H. Lin, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4), article 52, August, 2009.

·         T-trees: A Tree-Based Representation for Temporal and Three-Dimensional Floorplanning, P.-H. Yuh,   C.-L. Yang, Y.-W. Chang, in ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(4), article 51, August, 2009.

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, Y.-J. Chen, C.-L. Yang and Y.-S. Chang, in Journal of Systems Architecture, 55(5-6), 299-309, May, 2009.

·         A Predictive Shutdown Technique for GPU Shader Processors, P.-H. Wang, Y.-M. Chen, C.-L. Yang and Y.-J. Cheng, in IEEE Computer Architecture Letters, 8(1), 9-12, 2009.

·         A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters, -W, Wang, S.-S Yang, H.-M, Chen, C.-L, Yang, W.-J, Ling, in Journal Signal Processing Systems, 57(2), 195-211, November, 2009.

·         Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs, Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang, IEEE Trans. on CAD of Integrated Circuits and Systems27(4): 643-653 (2008)

·         BioRoute: A Network-Flow Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips, -H. Yuh, C.-L. Yang, and Y.-W. Chang, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(11), 1928-1941, 2008

·         Energy-Aware Flash Memory Management in Virtual Memory System, -H. Lin, C.-L. Yang, H.-W., Tseng, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(8), 952-964, August, 2008.

·         Placement of Defect-Tolerant Digital Microfluidic Biochips, -H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Journal on Emerging Technologies in Computing Systems (JETC), 3(3), article 13, November, 2007.

·         Temporal Floorplanning Using the Three Dimensional Transitive Closure SubGraph, -H. Yuh, C.-L. Yang, and Y.-W. Chang, in ACM Transaction on Design Automation of Electronic Systems (TODAES), 12(4), article 37, September, 2007..

·         Software-Controlled Cache Architecture for Energy Efficiency, -L. Yang, H.-W. Tseng, C.-C. Ho, J.-L. Wu, in IEEE Transaction on Circuits and Systems for Video Technology, 15(5), 634-644, May, 2005.

·         Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications, -L. Yang, A. R. Lebeck, H.-W. Tseng, and C.-H. Lee, in ACM Transacations on Architecture and Code Optimization, 1(4),  445-475, December, 2004.

·         Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero, Y,-J, Chang, F. Lai and C.-L Yang, in IEEE Transactions on Very Large Intergration (VLSI) Systems, 12(8), August, 2004.

·         Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C.-L. Yang, B. Sano, and A. R. Lebeck, in IEEE Transactions on Computers, 49(9), 934-946, September, 2000.

 

    Conference Papers

·         Latency Sensitivity-Based Cache Partitionig for Heterogeneous Multi-core Architecture, Po-Han Wong, Cheng-Hsuan Li, Chia-Lin Yang, in Proceedings of the 52th Annual Design Automation Conference (DAC’16), Austin, Texas, USA, June, 2016

·         MCSSim: A memory channel storage simulator, Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li, in Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC’16), Macao, Feb., 2016.

·         Fine-grained write scheduling for PCM performance improvement under write power budget, Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED ‘15), Rome, Italy, September, 2015

·         Improving DRAM latency with dynamic asymmetric subarray, Shih-Lien Lu,Ying-Chen Lin, Chia-Lin Yang,  in Proceedings of IEEE International Symposium on Microarchitecture (Micro’15), Waikiki, Hawaii,USA, December

·         A buffer cache architecture for smartphones with hybrid DRAM/PCM memory, Ye-Jyun Lin,Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, In Proceedings of 4th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA’16), Hong Kong, 2015

·         Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs, Yi-Jung Chen,Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu, in Proceedings of  ACM Research in Adaptive and Convergent Systems (RACS’15),  2015

·         Full system simulation framework for integrated CPU/GPU architecture, Po-Han Wang,Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April, 2014

·         NVM Duet: Unified Working Memory and Persistent Store Architecture, Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang*, Shun-Chih Yu, Cheng-Yuan Michael Wang, 2014, March, in Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '14), Salt Lake City, USA.

·         Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs, Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li, in Proceedings of the 50th Annual Design Automation Conference (DAC’14), San Fransisco, USA, June, 2014

·         Thermal coupling aware task migration using neighboring core search for many-core systems, Hitoshi Mizunuma,Yi-Chang Lu, Chia-Lin Yang, VLSI-DAT 2013: 1-4

·         Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs, Ping-Sheng Lin,Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED ‘13), WIP, Beijing, China, September, 2013

·         DuraCache: A Durable SSD Cache Using MLC NAND Flash, Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen, in Proceedings of the 50th Annual Design Automation Conference (DAC’13), Austin, USA, June, 2013

·         Distributed Memory Interface Synthesis for Network-on-Chips with 3-D Stacked DRAMs, Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD’12),  San Jose, USA, November, 2012.

·         SECRET: Selective Error Correction for Refresh Energy reducTion in DRAMs, Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang and Michael Wang, in Proceedings of the IEEE International Conference on Computer Design (ICCD’12), Sep., 2012.

·         Age-based PCM wear leveling with nearly zero search cost, Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang, in Proceedings of ACM/IEEE Design Automation Conference (DAC '12), San Franciso, CA, June, 2012.

·         A cycle-level SIMT-GPU simulation framework, Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’12), New Brunswick, NJ, April 2012.

·         Optimizing NAND Flash-Based SSDs via Retention Relaxation, Ren-Shuo Liu, Chia-Lin Yang, Wei Wu, in Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST '12), San Jose, CA, USA, Feb., 2012.

·         Memory Access Aware Power Gating for MPSoCs, Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang and Naehyuck Chang, in Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC), Feb., 2012.

·         A SAT-based routing algorithm for cross-referencing biochips, Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang, in Proceedings of the IEEE System Level Interconnect Prediction (SLIP), June, 2011.

·         Memory Latency Reduction via Thread Throttling, H. -Y Cheng, C.-H Lin, J. Lee , C.-L Yang, in Proceedings of IEEE International Symposium on Microarchitecture (Micro’10), Atlanta, Georgia, USA, December.

·         Hierarchical Memory Scheduling for Multimedia MPSoCs,-J Lin, C.-L Yang, T.-J Lin, J.-W Huang and N. Chang, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD’2010) , San Jose, USA, Nov, 2010.

·         Parallelization and Characterization of GARCH Option Pricing on GPUs, R.-S. Liu, Yun-Cheng Tsai, Chia-Lin Yang, Proceedings of IEEE International Symposium on Workload Characterization (IISWC’2010) , Atlanta, Georgia, USA, December

·         Dynamic Thermal Management for Networked Embedded Systems under Harsh Ambient Temperature Variation, Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang (ISLPED’10), Austin, TX, USA, August, 2010

·         PM-COSYN: PE and Memory Co-Synthesis for MPSoCs hermal Modeling for 3D-ICs with Integrated Microchannel Cooling, Y.-J. Chen, C.-L. Yang and P.-H. Wang, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '10), Dresden, Germany, March, 2010.

·         Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling, Mizunuma, C.-L. Yang, Y.-C. Lu, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD '09) , San Jose, CA, USA, November,  2009, Best  Paper Nomination.

·         PPT: Joint Performance/Power/Thermal Management of DRAM Memory for Multi-Core Systems, C.-H. Lin,  C.-L. Yang, K.-J. King, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '09), San Francisco, CA, USA, August, 2009, Best Paper Award.

·         Content-Aware Energy Prediction for Video Streaming in Mobile Devices, -C. Li, H.-H. Li, H.-L. Li, C.-L. Yang, in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April, 2009.

·         A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips, -H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, in Proceedings of ACM/IEEE Design Automation conference (DAC’08), Anaheim, CA, USA, June, 2008 (EI) (acceptance rate: 23%, 147/239).

·         Thermal coupling aware task migration using neighboring core search for many-core systems, Shao-Yi Chien,Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen, ICME 2007: 9

·         Efficient obstacle-avoiding rectilinear steiner tree construction, Chung-Wei Lin,Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang, ISPD 2007: 127-134

·         Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAs, C-F. Li, P-H. Yuh. C-L. Yang and Y-W. Chang, in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '07), Portland, USA, August, 2007.

·         Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, -H. Yuh, C.-L. Yang, ans Y.-W. Chang, in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD'07),San Jose, CA, November, 2007.

·         Cache Leakage Control Mechanism for Hard Real-Time Systems, -W. Chi, Y.-J. Chen, and C.-L. Yang, in Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '07), Saizburg, Austria, September, 2007.

·         Energy-Efficient Real-Time Task Scheduling with Task Rejection, -J. Chen, T.-W. Kuo, C.-L. Yang and K.-J. King, in Proceedings of Design, Automation & Test in Europe (DATE '07), Nice, France, April, 2007.

·         An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design, -H. Hung, Y.-J. Chen, C.-L. Yang, Y.-S. Chang, Alan P. Su, in Proceedings of 22nd Annual ACM Symposium on Applied Computing (SAC '07), Seoul, Korea, March, 2007.

·         Branch Behavior Characterization for Multimedia Applications, Chia-Lin Yang,Shun-Ying Wang, Yi-Jung Chen, Asia-Pacific Computer Systems Architecture Conference 2006: 523-530

·         An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage, -W. Tseng, H.-L. Li, and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006.

·         Hierarchical Value Cache Encoding for Off-chip Data Bus, -H. Lin and C.-L. Yang, in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '06), Tegernsee, Germany, October, 2006.

·         Placement of Digital Microfluidic Biochips Using the T-Tree Formuation, P-H. Yuh, C.-L. Yang,and Y.-W. Changn, in Proceedings of ACM/IEEE Design Automation Conference (DAC '06), San Franciso, CA, July, 2006.

·         A Space Efficient Caching Mechanism for Flash Memory Address Translation, -H. Wu, T.-W Kuo and C.-L Yan, in Proceedings of IEEE International Symposium on Object and component-oriented Real-time distributed Computing (ISORC '06), Gyeongju, Korea, April, 2006.

·         Cache Leakage Management for Multi-programming Workloads, -. Chen, C.-L. Yang, S.-H. Hung, in Proceedings of Asia-Pacific Computer Systems Architecture Conference (ACSAC '05), Singapore, October, 2005.

·         Reconfigurable Platform for Content Science Research, -S. Shih, C.-L. Yang, M.-K. Ku, T.-W. Kuo, S.-Y. Chien,Y.-W. Chang, L.-G. Chen, in Proceedings of Embedded and Real-Time Computing Systems and Applications (RTCSA'05), Hong Kong, August, 2005.

·         Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration, -W. Wu, C.-L. Yang, P.-H. Yuh,Y.-W. Chang, in Proceedings of the 2005 international symposium on Low power electronics and design (ISLPED '05), Sandiego, USA, August, 2005.

·         Phase-Aware I-Cache Size Synthesis with QoS Consideration, -J. Chen, C.-L. Yang, E.-K. Lin, in Proceedings of Asia and South Pacific International Conference on Embedded SoCs (ASPICES '05), Banagolore, India, July, 2005.

·         Workload Characterization of the H.264/AVC Decoder, -L. Yang, in Proceedings of the 5th IEEE Pacific-Rim Conference on Multimedia (PCM '04), Springer-Verlag, Japan, November, 2004.

·         Temporal Floorplanning using T-tree Formulation, -H. Yu, C.-L. Yang andY.-W. Chang, in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), San Jose, November, 2004.

·         Energy-Efficient Flash Memory Storage Systems with an Interrupt Emulation Mechanism, -H. Wu, T.-W Kuo and C.-L Yang, in Proceedings of IEEE/ACM International Conference on Hardware/Software odesign and System Synthesis (CODES + ISSS '04),Stockholm, Sweden, September, 2004.

·         HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction, -L. Yang and C.-H. Lee, in Proceedings of IEEE/ACM Internatioanl Symposium on Low Power Electronics and Design (ISLPED '04), NewPort Beach, California, August, 2004.

·         Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations, -J. Chen, H.-R. Hsu, K.-H. Chuang, C.-L. Yang, A.-C. Pang and T.-W. Kuo, in Processdings of 16th Euromicro Conferecne on Real-Time Systems (ECRTS'04), Catania, Italy, June, 2004.

·         Profit-Driven Uniprocessor Scheduling with Energy and Timing Constraints, -J. Chen, T.-W. Kuo and C.-L. Yang, in Proceedings of the in Proceedings of 19nd Annual ACM Symposium on Applied Computing (SAC '04), Nicosia, Cyprus, March, 2004.

·         Value-Conscious Cache: Simple Technique for Reducing Cache Access Power, -J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the Design, Automation and Test in Europe, Feburary (DATE '04), Paris, France, February, 2004.

·         Temporal Floorplanning Using 3D-subTCG, -H. Yuh, C.-L. Yang andY.-W. Chang, in Proceedings of 9th Asia and South Pacific Design Automation Conference (ASP-DAC'04), Japan, Janury, 2004.

·         Smart Cache: An Energy-Efficient D-Cache for a Software MPEG-2 Video Decoder, -L. Yang, H.-W. Tseng and C.-C. Ho, in Proceedings of the IEEE ICICS-PCM, Singapore, December 2003.

·         A Power-Ware SWRD Cell for Reducing Cache Write Power, -J. Chang, C.-L. Yang and F.-P. Lai, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design.(ISPLED '03), Seoul, Korea, August, 2003.

·         Using Intel Streaming SIMD Extensions for 3D Geometry Processing, Ma and C.-L. Yang, in Proceedings of the 3th IEEE Pacific-Rim Conference on Multimedia (PCM '02), Springer-Verlag, Taiwan, December, 2002.

·         A Programmable Memory Hierarchy for Prefetching Linked Data Structures, -L. Yang and A. R. Lebeck, in Proceedings of the 4th International Symposium on High Performance Computing (ISHPC-IV), Springer-Verlag, Japan, May, 2002.

·         Push vs. Pull: Data Movement for Linked Data Structures, -L. Yang and A. R. Lebeck, in Proceedings of International Conference on Supercomputing (ICS '00), May, 2000.

·         Annotated Memory References: A Mechanism for Informed Cache Management, R. Lebeck, D. R. Raymond, C.-L. Yang, M. S. Thottethodi, in Proceedings of Euro-Par '99, August, 1999. (Short Version).

·         Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, C.-L. Yang, B. Sano, and A. R. Lebeck,  in Proceedings of ACM/IEEE International Symposium on Microarchitecture (MICRO '98), November, 1998.

 

 Technical Reports

·         HotSpot Cache: Saving I-Cache Energy with Dynamic Program Hot Spot Detection for Multimedia Applications, C.-L. Yang, C.-H. Lee, In Technical Report (TK-03-03) of Department of Computer Science and Information Engineering,National Taiwan University.