BOOK
2004
"Speculative Execution in High Performance Computer Architectures,"
J. Lin, W. Hsu, and P. Yew,
Chapter 12, 2004.
[Link]
Journal
2016
"Optimizing Control Transfer and Memory Virtualization in Full System Emulators."
Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu
ACM Transactions on Architecture and Code Optimization (TACO),
12(4): 47:1-47:24 2016.
Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu
ACM Transactions on Architecture and Code Optimization (TACO),
12(4): 47:1-47:24 2016.
2015
"Automatic validation for binary translation,"
Jiunn-Yeu Chen, Wuu Yang, Bor-Yeh Shen, Yuan-Jia Li, Wei-Chung Hsu,
Computer Languages, Systems & Structures 43: 96-115 (2015)
"A dynamic binary translation system in a client/server environment,"
Chun-Chen Hsu, Ding-Yong Hong, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu,
Journal of Systems Architecture - Embedded Systems Design 61(7): 307-319 (2015)
"An Adaptive Heterogeneous Runtime Framework for Irregular Applications,"
Chih-Chen Kao, Wei-Chung Hsu,
Signal Processing Systems 80(3): 245-259 (2015)
Jiunn-Yeu Chen, Wuu Yang, Bor-Yeh Shen, Yuan-Jia Li, Wei-Chung Hsu,
Computer Languages, Systems & Structures 43: 96-115 (2015)
"A dynamic binary translation system in a client/server environment,"
Chun-Chen Hsu, Ding-Yong Hong, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu,
Journal of Systems Architecture - Embedded Systems Design 61(7): 307-319 (2015)
"An Adaptive Heterogeneous Runtime Framework for Irregular Applications,"
Chih-Chen Kao, Wei-Chung Hsu,
Signal Processing Systems 80(3): 245-259 (2015)
2014
"An Adaptive Heterogeneous Runtime Framework for Irregular Applications,"
C. Kao and W. Hsu,
Journal of Signal Processing Systems for Signal, Image, and Video Technology, Springer, July, 2014
July 2014.
[Link]
"Dynamic Binary Translation for Multi-Threaded Programs with Shared Code Cache on Multi-Cores,"
C. Liu, J. Chen, W. Yang, and W. Hsu,
Journal of Electronic Science and Technology,
vol. 12, no. 4, December 2014.
[Link]
"A Retargetable Static Binary Translator for the ARM Architectures,"
B. Shen, W. Yang, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 11, Iss. 2, No. 18, June 2014.
[Link]
"Efficient and Retargetable Dynamic Binary Translation on Multicores,"
D. Hung, J. Wu, P. Yew, W. Hsu, C. Hsu, P. Liu, C. Wang, and Y. Chung,
IEEE Transactions on Parallel and Distributed Systems (TPDS),
Vol. 25, Iss. 3, No. 3, Pp. 622-632, March 2014.
[Link]
"Extended Instruction Exploration for Multiple-Issue Architectures,"
I. Wu, J. Shann, W. Hsu, and C. Chung,
ACM Transactions on Embedded Computing Systems (TECS),
Vol. 13, Iss. 4, No. 92, February 2014.
[Link]
C. Kao and W. Hsu,
Journal of Signal Processing Systems for Signal, Image, and Video Technology, Springer, July, 2014
July 2014.
[Link]
"Dynamic Binary Translation for Multi-Threaded Programs with Shared Code Cache on Multi-Cores,"
C. Liu, J. Chen, W. Yang, and W. Hsu,
Journal of Electronic Science and Technology,
vol. 12, no. 4, December 2014.
[Link]
"A Retargetable Static Binary Translator for the ARM Architectures,"
B. Shen, W. Yang, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 11, Iss. 2, No. 18, June 2014.
[Link]
"Efficient and Retargetable Dynamic Binary Translation on Multicores,"
D. Hung, J. Wu, P. Yew, W. Hsu, C. Hsu, P. Liu, C. Wang, and Y. Chung,
IEEE Transactions on Parallel and Distributed Systems (TPDS),
Vol. 25, Iss. 3, No. 3, Pp. 622-632, March 2014.
[Link]
"Extended Instruction Exploration for Multiple-Issue Architectures,"
I. Wu, J. Shann, W. Hsu, and C. Chung,
ACM Transactions on Embedded Computing Systems (TECS),
Vol. 13, Iss. 4, No. 92, February 2014.
[Link]
2013
"The Design and Implementation of Heterogeneous Multi-Core for Energy-Efficient Speculative Thread Execution,"
Y. Luo, A. Zhai, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 10, Iss. 4, No. 26, December 2013.
[Link]
Y. Luo, A. Zhai, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 10, Iss. 4, No. 26, December 2013.
[Link]
2012
"Effectiveness of Compiler Directed Prefetching on Data Mining Benchmarks,"
V. Mekkat, R. Natarajan, W. Hsu, and A. Zhai,
Journal of Circuits, Systems, and Computers (JCSC),
Vol. 21, Iss. 2, April 2012.
[Link]
V. Mekkat, R. Natarajan, W. Hsu, and A. Zhai,
Journal of Circuits, Systems, and Computers (JCSC),
Vol. 21, Iss. 2, April 2012.
[Link]
2011
"Efficient and Effective Misaligned Data Access Handling in a Dynamic Binary Translation System,"
J. Li, C. Wu, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 8, Iss. 2, No. 7, July 2011.
[Link]
J. Li, C. Wu, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 8, Iss. 2, No. 7, July 2011.
[Link]
2007
"CIM: A Reliable Metric for Evaluating Program Phase Classifications,"
S. V. Kodakara, J. Kim, D. J. Lilja, D. Hawkins, W. Hsu, and P. Yew,
IEEE Computer Architecture Letters (CAL),
Vol. 6, Iss. 1, No. 1, Pp. 9-12, January 2007 - June 2007.
[Link]
S. V. Kodakara, J. Kim, D. J. Lilja, D. Hawkins, W. Hsu, and P. Yew,
IEEE Computer Architecture Letters (CAL),
Vol. 6, Iss. 1, No. 1, Pp. 9-12, January 2007 - June 2007.
[Link]
2006
"Recovery Code Generation for General Speculative Optimizations,"
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 3, Iss. 1, Pp. 67-89, March 2006.
[Link]
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 3, Iss. 1, Pp. 67-89, March 2006.
[Link]
2004
"A Compiler Framework for Speculative Optimizations,"
J. Lin, T. Chen, W. Hsu, P. Yew, R. Ju, T. Ngai, and S. Chan,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 1, Iss. 3, Pp. 247-271, September 2004.
[Link]
"Design and Implementation of a Lightweight Dynamic Optimization System,"
J. Lu, H. Chen, P. Yew, and W. Hsu,
Journal of Instruction-Level Parallelism (JILP),
Vol.6, 2004.
[Link]
J. Lin, T. Chen, W. Hsu, P. Yew, R. Ju, T. Ngai, and S. Chan,
ACM Transactions on Architecture and Code Optimization (TACO),
Vol. 1, Iss. 3, Pp. 247-271, September 2004.
[Link]
"Design and Implementation of a Lightweight Dynamic Optimization System,"
J. Lu, H. Chen, P. Yew, and W. Hsu,
Journal of Instruction-Level Parallelism (JILP),
Vol.6, 2004.
[Link]
1998
"A Performance Study of Instruction Cache Prefetching Methods,"
W. Hsu and J. Smith,
IEEE Transactions on Computers (ToC),
Vol.47, Iss.5, Pp. 497-508, May 1998.
[Link]
W. Hsu and J. Smith,
IEEE Transactions on Computers (ToC),
Vol.47, Iss.5, Pp. 497-508, May 1998.
[Link]
1997
"When Caches Aren't Enough: Data Prefetching Techniques,"
S. P. Vander Wiel, D. J. Lilja, and W. Hsu,
IEEE Computer Society,
Vol. 30, Iss. 7, Pp. 23-30, July 1997.
[Link]
S. P. Vander Wiel, D. J. Lilja, and W. Hsu,
IEEE Computer Society,
Vol. 30, Iss. 7, Pp. 23-30, July 1997.
[Link]
1993
"Towards Efficient Scalar Hardware for Highly Vectorizable Applications,"
S. Vayapeyam and W. Hsu,
Journal of Parallel and Distributed Computing (JPDC),
Vol. 19, Iss. 3, Pp. 147-162, November 1993.
[Link]
S. Vayapeyam and W. Hsu,
Journal of Parallel and Distributed Computing (JPDC),
Vol. 19, Iss. 3, Pp. 147-162, November 1993.
[Link]
1990
"The Use of Intermediate Memories for Low-Latency Memory Access in Supercomputer Scalar Units,"
G. Sohi and W. Hsu,
Journal of Supercomputing (JoS),
Vol. 4, Iss. 1, Pp. 5-21, March 1990.
[Link]
G. Sohi and W. Hsu,
Journal of Supercomputing (JoS),
Vol. 4, Iss. 1, Pp. 5-21, March 1990.
[Link]
1989
"On the Minimization of Loads/Stores in Local Register Allocation,"
W. Hsu, C. Fischer, and J. Goodman,
IEEE Transactions on Software Engineering (TSE),
Vol. 15, Iss. 10, Pp. 1252-1260, October 1989.
[Link]
W. Hsu, C. Fischer, and J. Goodman,
IEEE Transactions on Software Engineering (TSE),
Vol. 15, Iss. 10, Pp. 1252-1260, October 1989.
[Link]
Conference
2016
"A pipeline-based runtime technique for improving Ray-Tracing on HSA-compliant systems."
Chih-Chen Kao, Yu-Tsung Miao, Wei-Chung Hsu
IEEE International Conference on MultiMedia and Expo (ICME) 2016: 1-6
"Exploiting Longer SIMD Lanes in Dynamic Binary Translation"
Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu
IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS-22 2016),
Best Paper Award
"HSAemu 2.0: Full System Emulation for HSA platforms with Soft-MMU"
Hao-Che Hsu, Chih Wei Yeh, Shih-Hao Hung, Wei-Chung Hsu, Chung-Ta King, Yeh-Ching Chung
ACM RACS 2016 : 2016 Research in Adaptive and Convergent Systems,
"Building a KVM-based Hypervisor for a Heterogeneous System Architecture Compliant System. "
Yu-Ju Huang, Hsuan-Heng Wu, Yeh-Ching Chung, Wei-Chung Hsu
Proceedings of the 12th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE'2016)
Best Paper Award
Chih-Chen Kao, Yu-Tsung Miao, Wei-Chung Hsu
IEEE International Conference on MultiMedia and Expo (ICME) 2016: 1-6
"Exploiting Longer SIMD Lanes in Dynamic Binary Translation"
Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu
IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS-22 2016),
Best Paper Award
"HSAemu 2.0: Full System Emulation for HSA platforms with Soft-MMU"
Hao-Che Hsu, Chih Wei Yeh, Shih-Hao Hung, Wei-Chung Hsu, Chung-Ta King, Yeh-Ching Chung
ACM RACS 2016 : 2016 Research in Adaptive and Convergent Systems,
"Building a KVM-based Hypervisor for a Heterogeneous System Architecture Compliant System. "
Yu-Ju Huang, Hsuan-Heng Wu, Yeh-Ching Chung, Wei-Chung Hsu
Proceedings of the 12th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE'2016)
Best Paper Award
2015
"Improving SIMD code generation in QEMU,"
Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu,
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE-15 2015)
"Runtime techniques for efficient Ray-Tracing on heterogeneous systems,"
Chih-Chen Kao, Wei-Chung Hsu,
IEEE International Conference on Digital Signal Processing (DSP 2015)
"HSPT: Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA System Virtual Machines,"
Zhe Wang, Jianjun Li, Chenggang Wu, Dongyan Yang, Zhenjiang Wang, Wei-Chung Hsu, Bin Li, Yong Guan,
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-11 2015), 53-64
Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu,
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE-15 2015)
"Runtime techniques for efficient Ray-Tracing on heterogeneous systems,"
Chih-Chen Kao, Wei-Chung Hsu,
IEEE International Conference on Digital Signal Processing (DSP 2015)
"HSPT: Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA System Virtual Machines,"
Zhe Wang, Jianjun Li, Chenggang Wu, Dongyan Yang, Zhenjiang Wang, Wei-Chung Hsu, Bin Li, Yong Guan,
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-11 2015), 53-64
2014
"HSAemu – A Full System Emulator for HSA Platforms,"
J. Ding, W. Hsu, B. Jeng, S. Hung, and Y. Chung,
International Conference on Hardware/Software Co-Design and System Synthesis (Abbreviation),
October 2014.
[Link]
"An Adaptive Heterogeneous Runtime for Irregular Applications in the Case of Ray-Tracing,"
C. Kao and W. Hsu,
11th IFIP International Conference on Network and Parallel Computing (NPC-11 2014),
Aug. 2014.
[Link]
"Efficient Memory Virtualization for Cross-ISA System Mode Emulation,"
C. Chang, J. Wu, W. Hsu, P. Liu, and P. Yew,
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-10 2014),
March 2014.
[Link]
"DBILL: An Efficient and Retargetable Dynamic Binary Instrumentation Framework using LLVM Backend,"
Y. Lyu, D. Hong, T. Wu, J. Wu, W. Hsu, P. Liu, and P. Yew,
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-10 2014),
March 2014.
[Link]
"Dynamic and Adaptive Calling Context Encoding,"
J. Li, C. Wu, W. Hsu, Z. Wang, and D. Xu,
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-12 2014),
February 2014.
[Link]
J. Ding, W. Hsu, B. Jeng, S. Hung, and Y. Chung,
International Conference on Hardware/Software Co-Design and System Synthesis (Abbreviation),
October 2014.
[Link]
"An Adaptive Heterogeneous Runtime for Irregular Applications in the Case of Ray-Tracing,"
C. Kao and W. Hsu,
11th IFIP International Conference on Network and Parallel Computing (NPC-11 2014),
Aug. 2014.
[Link]
"Efficient Memory Virtualization for Cross-ISA System Mode Emulation,"
C. Chang, J. Wu, W. Hsu, P. Liu, and P. Yew,
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-10 2014),
March 2014.
[Link]
"DBILL: An Efficient and Retargetable Dynamic Binary Instrumentation Framework using LLVM Backend,"
Y. Lyu, D. Hong, T. Wu, J. Wu, W. Hsu, P. Liu, and P. Yew,
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-10 2014),
March 2014.
[Link]
"Dynamic and Adaptive Calling Context Encoding,"
J. Li, C. Wu, W. Hsu, Z. Wang, and D. Xu,
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-12 2014),
February 2014.
[Link]
2013
"Effective Code Discovery for ARM/Thumb-1 Mixed ISA Binaries in a Static Binary Translator,"
J. Chen, B. Shen, Q. Ou, W. Yang, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-15 2013),
September 2013 - October 2013.
[Link]
"Improving Dynamic Binary Optimization Through Early-Exit Guided Code Region Formation,"
C. Hsu, P. Liu, J. Wu, P. Yew, D. Hong, W. Hsu, and C. Wang,
Proceedings of the 9th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-9 2013),
July 2013.
[Link]
J. Chen, B. Shen, Q. Ou, W. Yang, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-15 2013),
September 2013 - October 2013.
[Link]
"Improving Dynamic Binary Optimization Through Early-Exit Guided Code Region Formation,"
C. Hsu, P. Liu, J. Wu, P. Yew, D. Hong, W. Hsu, and C. Wang,
Proceedings of the 9th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE-9 2013),
July 2013.
[Link]
2012
"LLBT: An LLVM-Based Static Binary Translator,"
B. Shen, J. Chen, W. Yang, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASE-15 2012),
October 2012.
[Link]
"A Hybrid Just-In-Time Compiler for Android. Comparing JIT Types and the Result of Cooperation,"
G. Pérez, C. Kao, Y. Chung, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASE-15 2012),
October 2012.
[Link]
"An LLVM-Based hybrid binary translation system,"
B. Shen, T. You, W. Yang, and W. Hsu,
7th IEEE International Symposium on Industrial Embedded Systems (SIES-7 2012),
June 2012.
[Link]
”HQEMU: A Multi-Threaded and Retargetable Dynamic Binary Translator on Multicores,"
D. Hong, J. Wu, P. Yew, W. Hsu, C. Hsu, P. Liu, C. Wang, and Y. Chung,
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-10 2012),
April 2012.
[Link]
B. Shen, J. Chen, W. Yang, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASE-15 2012),
October 2012.
[Link]
"A Hybrid Just-In-Time Compiler for Android. Comparing JIT Types and the Result of Cooperation,"
G. Pérez, C. Kao, Y. Chung, and W. Hsu,
Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASE-15 2012),
October 2012.
[Link]
"An LLVM-Based hybrid binary translation system,"
B. Shen, T. You, W. Yang, and W. Hsu,
7th IEEE International Symposium on Industrial Embedded Systems (SIES-7 2012),
June 2012.
[Link]
”HQEMU: A Multi-Threaded and Retargetable Dynamic Binary Translator on Multicores,"
D. Hong, J. Wu, P. Yew, W. Hsu, C. Hsu, P. Liu, C. Wang, and Y. Chung,
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-10 2012),
April 2012.
[Link]
2011
"PQEMU: A Parallel System Emulator Based on QEMU,"
J. Ding, P. Chang. W. Hsu, and Y. Chung,
IEEE 17th International Conference on Parallel and Distributed Systems (ICPADS-17 2011),
December 2011.
[Link]
"A Method-Based Ahead-of-Time Compiler for Android Applications,"
C. Wang, Y. Chung, W. Hsu, W. Shih, H. Hsu, and C. Wu,
Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-14 2011),
October 2011,
[Link]
"LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends,"
C.Hsu, P. Liu, C. Wang, J. Wu, D. Hong, P. Yew, and W. Hsu,
Proceedings of the 40th International Conference on Parallel Processing (ICPP-40 2011),
September 2011.
[Link]
"Efficient and Effective Misaligned Data Access Handling in a Dynamic Binary Translation System,"
J. Li, C. Wu, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
July 2011.
[Link]
"Dynamic Register Promotion of Stack Variables,"
J. Li, C. Wu, and W. Hsu,
Proceedings of the 9th International Symposium on Code Generation and Optimization (CGO-9 2011),
April 2011.
[Link]
J. Ding, P. Chang. W. Hsu, and Y. Chung,
IEEE 17th International Conference on Parallel and Distributed Systems (ICPADS-17 2011),
December 2011.
[Link]
"A Method-Based Ahead-of-Time Compiler for Android Applications,"
C. Wang, Y. Chung, W. Hsu, W. Shih, H. Hsu, and C. Wu,
Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-14 2011),
October 2011,
[Link]
"LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends,"
C.Hsu, P. Liu, C. Wang, J. Wu, D. Hong, P. Yew, and W. Hsu,
Proceedings of the 40th International Conference on Parallel Processing (ICPP-40 2011),
September 2011.
[Link]
"Efficient and Effective Misaligned Data Access Handling in a Dynamic Binary Translation System,"
J. Li, C. Wu, and W. Hsu,
ACM Transactions on Architecture and Code Optimization (TACO),
July 2011.
[Link]
"Dynamic Register Promotion of Stack Variables,"
J. Li, C. Wu, and W. Hsu,
Proceedings of the 9th International Symposium on Code Generation and Optimization (CGO-9 2011),
April 2011.
[Link]
2010
"Energy Efficient Speculative Threads: Dynamic Thread Allocation in Same-ISA Heterogeneous Multicore Systems,"
Y. Luo, V. Packirisamy, W. Hsu, and A. Zhai,
Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques (PACT-19 2010),
September 2010.
[Link]
Y. Luo, V. Packirisamy, W. Hsu, and A. Zhai,
Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques (PACT-19 2010),
September 2010.
[Link]
2009
"Dynamic Performance Tuning for Speculative Threads,"
Y. Luo, V. Packirisamy, N. Mungre, A. Tarkas, A. Zhai, and W. Hsu,
Proceedings of the 36th International Symposium on Computer Architecture (ISCA-36 2009),
June 2009.
[Link]
"An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems,"
J. Li, C. Wu, and W. Hsu,
Proceedings of the 7th International Symposium on Code Generation and Optimization (CGO-7 2009),
March 2009.
[Link]
"Exploring Speculative Parallelism in SPEC2006,"
V. Packirisamy, A. Zhai, P. Yew, and W. Hsu,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2009),
April 2009.
[Link]
Y. Luo, V. Packirisamy, N. Mungre, A. Tarkas, A. Zhai, and W. Hsu,
Proceedings of the 36th International Symposium on Computer Architecture (ISCA-36 2009),
June 2009.
[Link]
"An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems,"
J. Li, C. Wu, and W. Hsu,
Proceedings of the 7th International Symposium on Code Generation and Optimization (CGO-7 2009),
March 2009.
[Link]
"Exploring Speculative Parallelism in SPEC2006,"
V. Packirisamy, A. Zhai, P. Yew, and W. Hsu,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2009),
April 2009.
[Link]
2007
"Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization,"
S. V. Kodakara, J. Kim, D. J. Lilja, W. Hsu, and P. Yew,
Proceedings of the IEEE International Symposium on Workload Characterization (IISWC 2007),
September 2007.
[Link]
"COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications,"
J. Kim, W. Hsu, and P. Yew,
International Conference on Parallel Processing (ICPP 2007),
September 2007.
[Link]
S. V. Kodakara, J. Kim, D. J. Lilja, W. Hsu, and P. Yew,
Proceedings of the IEEE International Symposium on Workload Characterization (IISWC 2007),
September 2007.
[Link]
"COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications,"
J. Kim, W. Hsu, and P. Yew,
International Conference on Parallel Processing (ICPP 2007),
September 2007.
[Link]
2006
"Supporting Speculative Multithreading on Simultaneous Multithreaded Processors,"
V. Packirisamy, S. Wang, A. Zhai, W. Hsu, and P. Yew,
13th International Conference on High Performance Computing (HiPC-13 2006),
December 2006.
[Link]
"Region Monitoring for Local Phase Detection in Dynamic Optimization Systems,"
A. Das, J. Lu, and W. Hsu,
Proceedings of the 4th IEEE/ACM International Symposium on Code Generation and Optimization (CGO-4 2006),
March 2006.
[Link]
V. Packirisamy, S. Wang, A. Zhai, W. Hsu, and P. Yew,
13th International Conference on High Performance Computing (HiPC-13 2006),
December 2006.
[Link]
"Region Monitoring for Local Phase Detection in Dynamic Optimization Systems,"
A. Das, J. Lu, and W. Hsu,
Proceedings of the 4th IEEE/ACM International Symposium on Code Generation and Optimization (CGO-4 2006),
March 2006.
[Link]
2005
"Dynamic Helper Threaded Prefetching on the SUN Ultra SPARC CMP Processor,"
J. Lu, A. Das, W. Hsu, K. Ngyuan, and S. Abraham,
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005),
November 2005.
[Link]
"Dynamic Code Region (DCR)-Based Program Phase Tracking and Prediction for Dynamic Optimizations,"
J. Kim, S. Kodakara, W. Hsu, D. J. Lilja, and P. Yew,
Proceedings of the 1s tInternational Conference on High Performance Embedded Architectures and Compilers (HiPEAC-1 2005),
November 2005.
[Link]
"Performance of Runtime Optimization on BLAST,"
A. Das, J. Lu, H. Chen, J. Kim, W. Hsu, P. Yew, and D. Chen,
Proceedings of the 3rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO-3 2005),
March 2005.
[Link]
"A General Compiler Framework for Speculative Optimization Using Data Speculative Code Motion,"
X. Dai, W. Hsu, A. Zhai, and P. Yew,
Proceedings of the 3rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO-3 2005),
March 2005.
[Link]
J. Lu, A. Das, W. Hsu, K. Ngyuan, and S. Abraham,
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005),
November 2005.
[Link]
"Dynamic Code Region (DCR)-Based Program Phase Tracking and Prediction for Dynamic Optimizations,"
J. Kim, S. Kodakara, W. Hsu, D. J. Lilja, and P. Yew,
Proceedings of the 1s tInternational Conference on High Performance Embedded Architectures and Compilers (HiPEAC-1 2005),
November 2005.
[Link]
"Performance of Runtime Optimization on BLAST,"
A. Das, J. Lu, H. Chen, J. Kim, W. Hsu, P. Yew, and D. Chen,
Proceedings of the 3rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO-3 2005),
March 2005.
[Link]
"A General Compiler Framework for Speculative Optimization Using Data Speculative Code Motion,"
X. Dai, W. Hsu, A. Zhai, and P. Yew,
Proceedings of the 3rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO-3 2005),
March 2005.
[Link]
2004
"A Compiler Framework for Recovery Code Generation in General Speculative Optimizations,"
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT-13 2004),
October 2004.
[Link]
"Data Dependence Profiling for Speculative Optimizations,"
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 13th International Conference on Compiler Construction (CC-13 2004),
March 2004.
[Link]
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT-13 2004),
October 2004.
[Link]
"Data Dependence Profiling for Speculative Optimizations,"
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 13th International Conference on Compiler Construction (CC-13 2004),
March 2004.
[Link]
2003
"The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System,"
J. Lu, H. Chen, R. Fu, W. Hsu, P. Yew, and D. Chen,
Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO-36 2003),
December 2003.
[Link]
"A Compiler Framework for Speculative Analysis and Optimizations,"
J. Lin, T. Chen, W. Hsu, P. Yew, and R. Ju, Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI 2003),
June 2003.
[Link]
"Dynamic Trace Selection Using Performance Monitoring Hardware Sampling,"
H. Chen, W. Hsu, J. Lu, P. Yew,and H. Chen,
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO-1 2003),
March 2003.
[Link]
"Speculative Register Promotion Using Advanced Load Address Table (ALAT),"
J. Lin, T. Chen, W. Hsu, and P. Yew,
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO-1 2003),
March 2003.
[Link]
J. Lu, H. Chen, R. Fu, W. Hsu, P. Yew, and D. Chen,
Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO-36 2003),
December 2003.
[Link]
"A Compiler Framework for Speculative Analysis and Optimizations,"
J. Lin, T. Chen, W. Hsu, P. Yew, and R. Ju, Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI 2003),
June 2003.
[Link]
"Dynamic Trace Selection Using Performance Monitoring Hardware Sampling,"
H. Chen, W. Hsu, J. Lu, P. Yew,and H. Chen,
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO-1 2003),
March 2003.
[Link]
"Speculative Register Promotion Using Advanced Load Address Table (ALAT),"
J. Lin, T. Chen, W. Hsu, and P. Yew,
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO-1 2003),
March 2003.
[Link]
2002
"An Empirical Study on the Granularity of Pointer Analysis in C Programs,"
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 15th Workshop on Languages and Compilers for Parallel Computing (LCPC-15 2002),
July 2002.
[Link]
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 15th Workshop on Languages and Compilers for Parallel Computing (LCPC-15 2002),
July 2002.
[Link]
1997
"Data Prefetch on the HP-PA8000,"
V. Santhenam, E. Gornish, and W. Hsu,
Proceedings of the 24th International Symposium on Computer Architecture (ISCA-24 1997),
June 1997.
[Link]
V. Santhenam, E. Gornish, and W. Hsu,
Proceedings of the 24th International Symposium on Computer Architecture (ISCA-24 1997),
June 1997.
[Link]
1996
"Instruction Scheduling for the HP-PA8000,"
D. Dunn and W. Hsu,
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-29 1996),
December 1996.
[Link]
D. Dunn and W. Hsu,
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-29 1996),
December 1996.
[Link]
1993
"Performance of Cached DRAM in Vector Supercomputers,"
W. Hsu and J. Smith,
Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA-20 1993),
May 1993.
[Link]
W. Hsu and J. Smith,
Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA-20 1993),
May 1993.
[Link]
1992
"On the Instruction-Level Characteristics of Inherently Scalar Code in Highly-Vectorized Scientific Applications,"
S. Vayapeyam and W. Hsu,
Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO-25 1992),
November 1992.
[Link]
"Prefetching in Supercomputer Instruction Caches,"
J. Smith and W. Hsu,
Proceedings Supercomputing (SC 1992),
November 1992.
[Link]
S. Vayapeyam and W. Hsu,
Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO-25 1992),
November 1992.
[Link]
"Prefetching in Supercomputer Instruction Caches,"
J. Smith and W. Hsu,
Proceedings Supercomputing (SC 1992),
November 1992.
[Link]
1991
"An Empirical Study of the Cray Y-MP processor using the Perfect Club Benchmarks,"
S. Vajapeyam, W. Hsu, and G. Sohi,
Proceedings of the 18th Annual International Symposium on Computer Architecture (ISCA-18 1991),
May 1991.
[Link]
S. Vajapeyam, W. Hsu, and G. Sohi,
Proceedings of the 18th Annual International Symposium on Computer Architecture (ISCA-18 1991),
May 1991.
[Link]
1990
"Future General Purpose Supercomputer Architecture,"
S. Vajapeyam, G. Sohi, and W. Hsu,
Proceedings Supercomputing (SC 1990),
November 1990.
[Link]
"Exploitation of Instruction-Level Parallelism in a Cray X-MP processor,"
S. Vajapeyam, G. Sohi, and W. Hsu,
Proceedings of the IEEE International Conference on Computer Design: VLSI in Computer & Processors (ICCD 1991),
September 1990.
[Link]
S. Vajapeyam, G. Sohi, and W. Hsu,
Proceedings Supercomputing (SC 1990),
November 1990.
[Link]
"Exploitation of Instruction-Level Parallelism in a Cray X-MP processor,"
S. Vajapeyam, G. Sohi, and W. Hsu,
Proceedings of the IEEE International Conference on Computer Design: VLSI in Computer & Processors (ICCD 1991),
September 1990.
[Link]
1998
"Code Scheduling and Register Allocation in Large Basic Blocks,"
J. Goodman and W. Hsu,
Proceedings of the International Conference on Supercomputing (ICS 1988),
Month 1998.
[Link]
J. Goodman and W. Hsu,
Proceedings of the International Conference on Supercomputing (ICS 1988),
Month 1998.
[Link]
1987
"WISQ: A Restartable Architecture Using Queues,"
A. Pleszkun, J. Goodman, and W. Hsu,
Proceedings of the 14th Annual International Symposium on Computer Architectures (ISCA-14 1987),
June 1987.
[Link]
A. Pleszkun, J. Goodman, and W. Hsu,
Proceedings of the 14th Annual International Symposium on Computer Architectures (ISCA-14 1987),
June 1987.
[Link]
1986
"On the Use of Registers vs. Cache to Minimize Memory Traffic,"
J. Goodman and W. Hsu,
Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA-13 1986),
June 1986.
[Link]
J. Goodman and W. Hsu,
Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA-13 1986),
June 1986.
[Link]
Other
2014
"Hardware-Assisted Memory Address Translation for Cross-ISA System Virtualization,"
C. Chang, J. Wu, W. Hsu, P. Liu, and P. Yew,
20th Workshop on Compiler Techniques and System Software for High-Performance and Embedded Computing (CTHPC-20 2014),
Month 2014.
[Link]
C. Chang, J. Wu, W. Hsu, P. Liu, and P. Yew,
20th Workshop on Compiler Techniques and System Software for High-Performance and Embedded Computing (CTHPC-20 2014),
Month 2014.
[Link]
2013
"Dynamic Binary Translation for Multi-Threaded Programs with Shared Code Cache on Multi-Cores,"
C. Liu, J. Chen, W. Yang, and W. Hsu,
National Computer Symposium (NCS 2013),
Month 2013.
[Link]
"HSAemu – A Full System Emulator for HSA Platform,"
J. Ding, Z. Guo, C. Kuo, W. Hsu, and Y. Chung,
AMD Developer Summit (APU 2013),
November 2013.
[Link]
"Automatic Validation for Static Binary Translation,"
J. Chen, B. Shen, Y. Li, W. Yang, and W. Hsu,
2nd Asia-Pacific Programming Languages and Compilers Workshop (APPLC-2 2013),
February 2013.
[Link]
C. Liu, J. Chen, W. Yang, and W. Hsu,
National Computer Symposium (NCS 2013),
Month 2013.
[Link]
"HSAemu – A Full System Emulator for HSA Platform,"
J. Ding, Z. Guo, C. Kuo, W. Hsu, and Y. Chung,
AMD Developer Summit (APU 2013),
November 2013.
[Link]
"Automatic Validation for Static Binary Translation,"
J. Chen, B. Shen, Y. Li, W. Yang, and W. Hsu,
2nd Asia-Pacific Programming Languages and Compilers Workshop (APPLC-2 2013),
February 2013.
[Link]
2012
"ARMvisor: System Virtualization for ARM,"
J. Ding, C. Lin, P. Chang, C. Tsang, W. Hsu, and Y. Chung,
Ottawa Linux Symposium (OLS),
July 2012.
[Link]
J. Ding, C. Lin, P. Chang, C. Tsang, W. Hsu, and Y. Chung,
Ottawa Linux Symposium (OLS),
July 2012.
[Link]
2011
"LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends,"
C. Hsu, P. Liu, C. Wang, J. Wu, D. Hong, P. Yew, and W. Hsu,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"A Method-Based Ahead-of-Time Compiler for Android Applications,"
C. Wang, Y. Chung, W. Hsu, W. Shih, H. Hsu, and C. Wu,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"A Parallel Dynamic Binary Translation Design for Multi-Core System Emulator,"
J. Ding, P. Chang, W. Hsu, and Y. Chung,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"ARMvisor: System Virtualization for ARM,"
J. Ding, S. Li, W. Hsu, and Y. Chung,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
C. Hsu, P. Liu, C. Wang, J. Wu, D. Hong, P. Yew, and W. Hsu,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"A Method-Based Ahead-of-Time Compiler for Android Applications,"
C. Wang, Y. Chung, W. Hsu, W. Shih, H. Hsu, and C. Wu,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"A Parallel Dynamic Binary Translation Design for Multi-Core System Emulator,"
J. Ding, P. Chang, W. Hsu, and Y. Chung,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
"ARMvisor: System Virtualization for ARM,"
J. Ding, S. Li, W. Hsu, and Y. Chung,
11th Workshop on Compiler Techniques for High-Performance and Embedded Computing (CTHPC-11 2011),
June 2011.
[Link]
2010
"Register Reassignment for Mixed- Width ISAs is an NP-Complete Problem,"
B. Shen, W. Hsu, and W. Yang.
1st International Multi-Conference on Complexity, Informatics and Cybernetics (IMCIC-1 2010),
April 2010.
[Link]
"Performance characterization of data mining benchmarks,"
V. Mekkat, R. Natarajan, W. Hsu, and A. Zhai,
Proceedings of the 14th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-14 2010), held in conjunction with the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-15 2010),
March 2010.
[Link]
B. Shen, W. Hsu, and W. Yang.
1st International Multi-Conference on Complexity, Informatics and Cybernetics (IMCIC-1 2010),
April 2010.
[Link]
"Performance characterization of data mining benchmarks,"
V. Mekkat, R. Natarajan, W. Hsu, and A. Zhai,
Proceedings of the 14th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-14 2010), held in conjunction with the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-15 2010),
March 2010.
[Link]
2009
"Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor,"
J. Wang, I. Wu, Y. Chen, J. Shann, W. Yang, and W. Hsu,
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering (CSE-12 2009),
August 2009.
[Link]
"Program Type Recognition for Compiler Optimization,"
T. Hung, J. Chen, W. Yang, and W. Hsu,
7th Workshop on Optimizations for DSP and Embedded Systems (ODES-7 2009), held in conjunction with the 7th Annual IEEE/ACM International
Symposium on Code Generation and Optimization (CGO-7 2009),
Month 2009.
[Link]
J. Wang, I. Wu, Y. Chen, J. Shann, W. Yang, and W. Hsu,
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering (CSE-12 2009),
August 2009.
[Link]
"Program Type Recognition for Compiler Optimization,"
T. Hung, J. Chen, W. Yang, and W. Hsu,
7th Workshop on Optimizations for DSP and Embedded Systems (ODES-7 2009), held in conjunction with the 7th Annual IEEE/ACM International
Symposium on Code Generation and Optimization (CGO-7 2009),
Month 2009.
[Link]
2008
"A New Approach for Improving Ported Java JIT Compilers for Embedded Systems,"
S. Huang, Y. Chen, J. Shann, W. Hsu, and W. Yang,
International Computer Symposium (ICS 2008),
November 2008.
[Link]
"A Static Binary Translator for Efficient Migration of ARM based Applications,"
J. Chen, W. Yang, J. Hung, C. Su, and W. Hsu,
6th Workshop on Optimizations for DSP and Embedded Systems (ODES-6 2008), held in conjunction with the 6th Annual IEEE/ACM International
Symposium on Code Generation and Optimization (CGO-6 2008),
Month 2008.
[Link]
S. Huang, Y. Chen, J. Shann, W. Hsu, and W. Yang,
International Computer Symposium (ICS 2008),
November 2008.
[Link]
"A Static Binary Translator for Efficient Migration of ARM based Applications,"
J. Chen, W. Yang, J. Hung, C. Su, and W. Hsu,
6th Workshop on Optimizations for DSP and Embedded Systems (ODES-6 2008), held in conjunction with the 6th Annual IEEE/ACM International
Symposium on Code Generation and Optimization (CGO-6 2008),
Month 2008.
[Link]
2007
"Entropy-Based Profile Characterization and Classification for Automatic Profile Management,"
J. Kim, W. Hsu, P. Yew, S. R. Nair, R. Y. Geva,
12th Asia-Pacific Computer Systems Architecture Conference (ACSAC-12 2007),
August 2007.
[Link]
"Dynamic Profile Driven Code Version Selection,"
P. Chuang, H. Chen, G. F. Hoflehner, D. M. Lavery, and W. Hsu,
Proceedings of the 11th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-11 2007),
Month 2007.
[Link]
"Reducing Queuing Stalls Caused By Data Prefetching,"
R. Fu, A. Zhai, P. Yew, W. Hsu, and J. Lu,
Proceedings of the 11th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-11 2007),
Month 2007.
[Link]
J. Kim, W. Hsu, P. Yew, S. R. Nair, R. Y. Geva,
12th Asia-Pacific Computer Systems Architecture Conference (ACSAC-12 2007),
August 2007.
[Link]
"Dynamic Profile Driven Code Version Selection,"
P. Chuang, H. Chen, G. F. Hoflehner, D. M. Lavery, and W. Hsu,
Proceedings of the 11th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-11 2007),
Month 2007.
[Link]
"Reducing Queuing Stalls Caused By Data Prefetching,"
R. Fu, A. Zhai, P. Yew, W. Hsu, and J. Lu,
Proceedings of the 11th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-11 2007),
Month 2007.
[Link]
2006
"A Study of the Performance Potential for Dynamic Instruction Hints Selection,"
R. Fu, J. Lu, A. Zhai, and W. Hsu,
11th Asia-Pacific Computer Systems Architecture Conference (ACSAC-11 2006),
September 2006.
[Link]
"Issues and Support for Dynamic Register Allocation,"
A. Das, A. Zhai, R. Fu, and W. Hsu,
11th Asia-Pacific Computer Systems Architecture Conference (ACSAC-11 2006),
September 2006.
[Link]
R. Fu, J. Lu, A. Zhai, and W. Hsu,
11th Asia-Pacific Computer Systems Architecture Conference (ACSAC-11 2006),
September 2006.
[Link]
"Issues and Support for Dynamic Register Allocation,"
A. Das, A. Zhai, R. Fu, and W. Hsu,
11th Asia-Pacific Computer Systems Architecture Conference (ACSAC-11 2006),
September 2006.
[Link]
2004
"Continuous Adaptive Object-Code Re-Optimization Framework,"
H. Chen, J. Lu, W. Hsu, and P. Yew,
9th Asia-Pacific Computer Systems Architecture Conference (ACSAC-9 2004)
December 2004,
[Link]
"On Speculative Optimizations Using Alias Profiling and Heuristics for C Programs,"
J. Lin, T. Chen, W. Hsu, and P. Yew,
3rd Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology (EPIC-3 2004), held in conjunction with the 2nd
Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-2 2004),
March 2004.
[Link]
H. Chen, J. Lu, W. Hsu, and P. Yew,
9th Asia-Pacific Computer Systems Architecture Conference (ACSAC-9 2004)
December 2004,
[Link]
"On Speculative Optimizations Using Alias Profiling and Heuristics for C Programs,"
J. Lin, T. Chen, W. Hsu, and P. Yew,
3rd Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology (EPIC-3 2004), held in conjunction with the 2nd
Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-2 2004),
March 2004.
[Link]
2002
"On the Impact of Naming Methods for Heap-Oriented Pointers in C Programs,"
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 6th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN-6 2002),
May 2002.
[Link]
"On the Predictability of Program Behavior Using Different Input Data Sets,"
W. Hsu, H. Chen, P, Yew, and D. Chen,
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6 2002), held in conjunction
with the 8th International Symposium on High-Performance Computer Architecture (HPCA-8 2002),
February 2002.
[Link]
T. Chen, J. Lin, W. Hsu, and P. Yew,
Proceedings of the 6th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN-6 2002),
May 2002.
[Link]
"On the Predictability of Program Behavior Using Different Input Data Sets,"
W. Hsu, H. Chen, P, Yew, and D. Chen,
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6 2002), held in conjunction
with the 8th International Symposium on High-Performance Computer Architecture (HPCA-8 2002),
February 2002.
[Link]
1997
"FMAC Code Optimization Issues,"
B. Blume and W. Hsu,
Proceedings of the 1st Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-1 1997), held in conjunction with the 3nd International Symposium on High-Performance Computer Architecture (HPCA-3 1997),
February 1997.
[Link]
B. Blume and W. Hsu,
Proceedings of the 1st Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-1 1997), held in conjunction with the 3nd International Symposium on High-Performance Computer Architecture (HPCA-3 1997),
February 1997.
[Link]
1996
"Data Prefetch in PA7200 and PA8000,"
W. Hsu,
Proceedings of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT 1996), held in conjunction with the 2nd International Symposium on High-Performance Computer Architecture (HPCA-2 1996),
February 1996.
[Link]
W. Hsu,
Proceedings of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT 1996), held in conjunction with the 2nd International Symposium on High-Performance Computer Architecture (HPCA-2 1996),
February 1996.
[Link]
1992
"On Memory Coherency in Parallel Processing,"
W. Hsu,
Proceedings of the 14th Modern Engineering and Technology Symposium (METS),
December 1992.
W. Hsu,
Proceedings of the 14th Modern Engineering and Technology Symposium (METS),
December 1992.
1990
"Aspects of Cache Memories for Cray Computers,"
W. Hsu,
Cray Technical Symposium,
Month 1990.
[Link]
W. Hsu,
Cray Technical Symposium,
Month 1990.
[Link]
Technical Report
2006
"Issues and Support for Dynamic Register Allocation,"
A. Das, R. Fu, A. Zhai, and W. Hsu,
Technical Report # 06-020, Department of Computer Science, University of Minnesota.
Month 2006.
A. Das, R. Fu, A. Zhai, and W. Hsu,
Technical Report # 06-020, Department of Computer Science, University of Minnesota.
Month 2006.
2005
"PASS: Program Structure Aware Stratified Sampling for Statistically Selecting Instruction Traces and Simulation Points,"
S. V. Kodakara, J. Kim. W. Hsu, D. J. Lilja, and P. Yew,
Technical Report # 05-044, Department of Computer Science, University of Minnesota,
December 2005.
"Implementation of Trace Optimization and Investigation of Advanced Load Optimization in ADORE,"
S. Joshi, W. Hsu, and P. Yew,
Technical Report # 05-027, Department of Computer Science, University of Minnesota,
July 2005.
"Dynamic Code Region-based Program Phase Classification and Transition Prediction,"
J. Kim, S. V. Kodakara, W. Hsu, D. J. Lilja, and P. Yew,
Technical Report # 05-021, Department of Computer Science, University of Minnesota,
May 2005.
S. V. Kodakara, J. Kim. W. Hsu, D. J. Lilja, and P. Yew,
Technical Report # 05-044, Department of Computer Science, University of Minnesota,
December 2005.
"Implementation of Trace Optimization and Investigation of Advanced Load Optimization in ADORE,"
S. Joshi, W. Hsu, and P. Yew,
Technical Report # 05-027, Department of Computer Science, University of Minnesota,
July 2005.
"Dynamic Code Region-based Program Phase Classification and Transition Prediction,"
J. Kim, S. V. Kodakara, W. Hsu, D. J. Lilja, and P. Yew,
Technical Report # 05-021, Department of Computer Science, University of Minnesota,
May 2005.
2004
"Dynamic Register Allocation for ADORE Runtime Optimization System,"
A. Saxena and W. Hsu,
Technical Report # 04-044, Department of Computer Science, University of Minnesota,
December 2004.
"Performance of Runtime Optimization on BLAST,"
A. Das, J. Lu, H. Chen, J. Kim, P. Yew, W. Hsu, and D. Chen,
Technical Report # 04-038, Department of Computer Science, University of Minnesota,
October 2004.
"PerfView: A Performance Monitoring and Visualization Tool for Intel Itanium Architecture,"
A. Lingamneni, A. Das, and W. Hsu,
Technical Report # 04-030, Department of Computer Science, University of Minnesota,
July 2004.
"A General Compiler Framework for Data Speculation Using DSCM,"
X. Dai, W. Hsu, and P. Yew,
Technical Report # 04-012, Department of Computer Science, University of Minnesota,
March 2004.
A. Saxena and W. Hsu,
Technical Report # 04-044, Department of Computer Science, University of Minnesota,
December 2004.
"Performance of Runtime Optimization on BLAST,"
A. Das, J. Lu, H. Chen, J. Kim, P. Yew, W. Hsu, and D. Chen,
Technical Report # 04-038, Department of Computer Science, University of Minnesota,
October 2004.
"PerfView: A Performance Monitoring and Visualization Tool for Intel Itanium Architecture,"
A. Lingamneni, A. Das, and W. Hsu,
Technical Report # 04-030, Department of Computer Science, University of Minnesota,
July 2004.
"A General Compiler Framework for Data Speculation Using DSCM,"
X. Dai, W. Hsu, and P. Yew,
Technical Report # 04-012, Department of Computer Science, University of Minnesota,
March 2004.
2003
"A Compiler Framework for Recovery Code Generation in General Speculative Optimizations,"
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
Technical Report # 03-051, Department of Computer Science, University of Minnesota,
December 2003.
J. Lin, W. Hsu, P. Yew, R. Ju, and T. Ngai,
Technical Report # 03-051, Department of Computer Science, University of Minnesota,
December 2003.
2002
"Phase Locality Detection Using a Branch Trace Buffer for Efficient Profiling in Dynamic Optimization,"
W. Hsu, H. Chen, P. Yew, and D. Chen,
Technical Report # 02-006, Department of Computer Science, University of Minnesota,
February 2002.
W. Hsu, H. Chen, P. Yew, and D. Chen,
Technical Report # 02-006, Department of Computer Science, University of Minnesota,
February 2002.
1987
"Register Allocation and Code Scheduling for Load/Store Architectures,"
W. Hsu,
Technical Report # 722, Department of Computer Science, University of Wisconsin–Madison,
October 1987.
W. Hsu,
Technical Report # 722, Department of Computer Science, University of Wisconsin–Madison,
October 1987.
1985
"Register Allocation for VLSI Processors,"
W. Hsu,
Technical Report # 619, Department of Computer Science, University of Wisconsin–Madison,
November 1985.
W. Hsu,
Technical Report # 619, Department of Computer Science, University of Wisconsin–Madison,
November 1985.
Patent
2008
"Method and Structure for Correlation-Based Prefetching,"
W.Hsu and Y. Chou,
US Patent # 7,457,923,
November 2008.
W.Hsu and Y. Chou,
US Patent # 7,457,923,
November 2008.
2003
"Hardware/Software System for Profiling Instructions and Selecting a Trace Using Branch History Information for Branch Prediction,"
W. Hsu and R. Benitez,
US Patent # 6,647,491,
November 2003.
W. Hsu and R. Benitez,
US Patent # 6,647,491,
November 2003.
2002
"System and Method Using a Hardware Embedded Run-Time Optimizer,"
W. Hsu and R. Benitez,
US Patent # 6,453,411 (US20030005271),
September 2002.
"Hardware System for Fetching Mapped Branch Target Instructions of Optimized Code Placed into a Trace Memory,"
W. Hsu and R. Benitez,
US Patent # 6,430,675,
August 2002.
"Hardware/Software System for Instruction Profiling and Trace Selection Using Branch History Information for Branch Predictions,"
W. Hsu and R. Benitez,
US Patent # 6,418,530,
July 2002.
W. Hsu and R. Benitez,
US Patent # 6,453,411 (US20030005271),
September 2002.
"Hardware System for Fetching Mapped Branch Target Instructions of Optimized Code Placed into a Trace Memory,"
W. Hsu and R. Benitez,
US Patent # 6,430,675,
August 2002.
"Hardware/Software System for Instruction Profiling and Trace Selection Using Branch History Information for Branch Predictions,"
W. Hsu and R. Benitez,
US Patent # 6,418,530,
July 2002.
2001
"System and Method Using Text Patching for Run-Time Optimization,"
W. Hsu and R. Benitez,
US Patent # 6,295,644,
September 2001.
"Efficient Mapping to Optimized Code for Processor Embedded Run-Time Optimizer,"
W. Hsu and L. Shah,
US Patent # 6,185,669,
February 2001.
W. Hsu and R. Benitez,
US Patent # 6,295,644,
September 2001.
"Efficient Mapping to Optimized Code for Processor Embedded Run-Time Optimizer,"
W. Hsu and L. Shah,
US Patent # 6,185,669,
February 2001.
2000
"Array Padding for Higher Memory Throughput in the Presence of Dirty Misses,"
W. Hsu,
US Patent # 6,041,393,
March 2000.
W. Hsu,
US Patent # 6,041,393,
March 2000.
1999
"Method and System for Optimizing Code,"
W. Hsu,
US Patent # 5,901,318,
May 1999.
W. Hsu,
US Patent # 5,901,318,
May 1999.
1998
"Optimizing Compiler Having Data Cache Prefetch Spreading,"
W. Hsu and L. Staley,
US Patent # 5,854,934,
December 1998.
"Method of Prefetching Data for References with Multiple Stride Directions,"
W. Hsu, A. Holler, and E. Gornish,
US Patent # 5,752,037,
May 1998.
W. Hsu and L. Staley,
US Patent # 5,854,934,
December 1998.
"Method of Prefetching Data for References with Multiple Stride Directions,"
W. Hsu, A. Holler, and E. Gornish,
US Patent # 5,752,037,
May 1998.